1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux-mx28.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <linux/mii.h>
21 DECLARE_GLOBAL_DATA_PTR;
26 int board_early_init_f(void)
28 /* IO0 clock at 480MHz */
29 mxs_set_ioclk(MXC_IOCLK0, 480000);
30 /* IO1 clock at 480MHz */
31 mxs_set_ioclk(MXC_IOCLK1, 480000);
33 /* SSP0 clock at 96MHz */
34 mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
35 /* SSP2 clock at 160MHz */
36 mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
39 mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
40 mxs_iomux_setup_pad(MX28_PAD_AUART3_TX__GPIO_3_13 |
41 MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
42 gpio_direction_output(MX28_PAD_AUART3_TX__GPIO_3_13, 0);
44 mxs_iomux_setup_pad(MX28_PAD_AUART3_RX__GPIO_3_12 |
45 MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP);
46 gpio_direction_output(MX28_PAD_AUART3_RX__GPIO_3_12, 0);
54 /* Adress of boot parameters */
55 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
62 return mxs_dram_init();
66 static int m28_mmc_wp(int id)
69 printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
73 return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10);
76 int board_mmc_init(bd_t *bis)
78 /* Configure WP as input. */
79 gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
80 /* Turn on the power to the card. */
81 gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
83 return mxsmmc_initialize(bis, 0, m28_mmc_wp, NULL);
89 #define MII_OPMODE_STRAP_OVERRIDE 0x16
90 #define MII_PHY_CTRL1 0x1e
91 #define MII_PHY_CTRL2 0x1f
93 int fecmxc_mii_postcall(int phy)
95 #if defined(CONFIG_ARIES_M28_V11) || defined(CONFIG_ARIES_M28_V10)
96 /* KZ8031 PHY on old boards. */
97 const uint32_t freq = 0x0080;
99 /* KZ8021 PHY on new boards. */
100 const uint32_t freq = 0x0000;
103 miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
104 miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
106 miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8100 | freq);
110 int board_eth_init(bd_t *bis)
112 struct mxs_clkctrl_regs *clkctrl_regs =
113 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
114 struct eth_device *dev;
117 ret = cpu_eth_init(bis);
121 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
122 CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
123 CLKCTRL_ENET_TIME_SEL_RMII_CLK);
125 #if !defined(CONFIG_ARIES_M28_V11) && !defined(CONFIG_ARIES_M28_V10)
126 /* Reset the new PHY */
127 gpio_direction_output(MX28_PAD_AUART2_RTS__GPIO_3_11, 0);
129 gpio_set_value(MX28_PAD_AUART2_RTS__GPIO_3_11, 1);
133 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
135 printf("FEC MXS: Unable to init FEC0\n");
139 ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
141 printf("FEC MXS: Unable to init FEC1\n");
145 dev = eth_get_dev_by_name("FEC0");
147 printf("FEC MXS: Unable to get FEC0 device entry\n");
151 ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
153 printf("FEC MXS: Unable to register FEC0 mii postcall\n");
157 dev = eth_get_dev_by_name("FEC1");
159 printf("FEC MXS: Unable to get FEC1 device entry\n");
163 ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
165 printf("FEC MXS: Unable to register FEC1 mii postcall\n");