board/amcc/yucca/yucca.c

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  * Port to AMCC-440SPE Evaluation Board SOP - April 2005
  24  *
  25  * PCIe supporting routines derived from Linux 440SPe PCIe driver.
  26  */
  27
  28 #include <common.h>
  29 #include <ppc4xx.h>
  30 #include <i2c.h>
  31 #include <asm/processor.h>
  32 #include <asm/io.h>
  33 #include <asm/4xx_pcie.h>
  34
  35 #include "yucca.h"
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39
  40 void fpga_init (void);
  41 void get_sys_info(PPC440_SYS_INFO *board_cfg );
  42 int compare_to_true(char *str );
  43 char *remove_l_w_space(char *in_str );
  44 char *remove_t_w_space(char *in_str );
  45 int get_console_port(void);
  46
  47 #define DEBUG_ENV
  48 #ifdef DEBUG_ENV
  49 #define DEBUGF(fmt,args...) printf(fmt ,##args)
  50 #else
  51 #define DEBUGF(fmt,args...)
  52 #endif
  53
  54 #define FALSE   0
  55 #define TRUE    1
  56
  57 int board_early_init_f (void)
  58 {
  59 /*----------------------------------------------------------------------------+
  60 | Define Boot devices
  61 +----------------------------------------------------------------------------*/
  62 #define BOOT_FROM_SMALL_FLASH           0x00
  63 #define BOOT_FROM_LARGE_FLASH_OR_SRAM   0x01
  64 #define BOOT_FROM_PCI                   0x02
  65 #define BOOT_DEVICE_UNKNOWN             0x03
  66
  67 /*----------------------------------------------------------------------------+
  68 | EBC Devices Characteristics
  69 |   Peripheral Bank Access Parameters       -   EBC_BxAP
  70 |   Peripheral Bank Configuration Register  -   EBC_BxCR
  71 +----------------------------------------------------------------------------*/
  72
  73 /*
  74  * Small Flash and FRAM
  75  * BU Value
  76  * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
  77  * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000
  78  * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000
  79  */
  80 #define EBC_BXAP_SMALL_FLASH            EBC_BXAP_BME_DISABLED   | \
  81                                         EBC_BXAP_TWT_ENCODE(7)  | \
  82                                         EBC_BXAP_BCE_DISABLE    | \
  83                                         EBC_BXAP_BCT_2TRANS     | \
  84                                         EBC_BXAP_CSN_ENCODE(0)  | \
  85                                         EBC_BXAP_OEN_ENCODE(0)  | \
  86                                         EBC_BXAP_WBN_ENCODE(0)  | \
  87                                         EBC_BXAP_WBF_ENCODE(0)  | \
  88                                         EBC_BXAP_TH_ENCODE(0)   | \
  89                                         EBC_BXAP_RE_DISABLED    | \
  90                                         EBC_BXAP_SOR_DELAYED    | \
  91                                         EBC_BXAP_BEM_WRITEONLY  | \
  92                                         EBC_BXAP_PEN_DISABLED
  93
  94 #define EBC_BXCR_SMALL_FLASH_CS0        EBC_BXCR_BAS_ENCODE(0xFF000000) | \
  95                                         EBC_BXCR_BS_16MB                | \
  96                                         EBC_BXCR_BU_RW                  | \
  97                                         EBC_BXCR_BW_8BIT
  98
  99 #define EBC_BXCR_SMALL_FLASH_CS2        EBC_BXCR_BAS_ENCODE(0xe7000000) | \
 100                                         EBC_BXCR_BS_16MB                | \
 101                                         EBC_BXCR_BU_RW                  | \
 102                                         EBC_BXCR_BW_8BIT
 103
 104 /*
 105  * Large Flash and SRAM
 106  * BU Value
 107  * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
 108  * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
 109  * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
 110 */
 111 #define EBC_BXAP_LARGE_FLASH            EBC_BXAP_BME_DISABLED   | \
 112                                         EBC_BXAP_TWT_ENCODE(7)  | \
 113                                         EBC_BXAP_BCE_DISABLE    | \
 114                                         EBC_BXAP_BCT_2TRANS     | \
 115                                         EBC_BXAP_CSN_ENCODE(0)  | \
 116                                         EBC_BXAP_OEN_ENCODE(0)  | \
 117                                         EBC_BXAP_WBN_ENCODE(0)  | \
 118                                         EBC_BXAP_WBF_ENCODE(0)  | \
 119                                         EBC_BXAP_TH_ENCODE(0)   | \
 120                                         EBC_BXAP_RE_DISABLED    | \
 121                                         EBC_BXAP_SOR_DELAYED    | \
 122                                         EBC_BXAP_BEM_WRITEONLY  | \
 123                                         EBC_BXAP_PEN_DISABLED
 124
 125 #define EBC_BXCR_LARGE_FLASH_CS0        EBC_BXCR_BAS_ENCODE(0xFF000000) | \
 126                                         EBC_BXCR_BS_16MB                | \
 127                                         EBC_BXCR_BU_RW                  | \
 128                                         EBC_BXCR_BW_16BIT
 129
 130 #define EBC_BXCR_LARGE_FLASH_CS2        EBC_BXCR_BAS_ENCODE(0xE7000000) | \
 131                                         EBC_BXCR_BS_16MB                | \
 132                                         EBC_BXCR_BU_RW                  | \
 133                                         EBC_BXCR_BW_16BIT
 134
 135 /*
 136  * FPGA
 137  * BU value :
 138  * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
 139  * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000
 140  */
 141 #define EBC_BXAP_FPGA                   EBC_BXAP_BME_DISABLED   | \
 142                                         EBC_BXAP_TWT_ENCODE(11) | \
 143                                         EBC_BXAP_BCE_DISABLE    | \
 144                                         EBC_BXAP_BCT_2TRANS     | \
 145                                         EBC_BXAP_CSN_ENCODE(10) | \
 146                                         EBC_BXAP_OEN_ENCODE(1)  | \
 147                                         EBC_BXAP_WBN_ENCODE(1)  | \
 148                                         EBC_BXAP_WBF_ENCODE(1)  | \
 149                                         EBC_BXAP_TH_ENCODE(1)   | \
 150                                         EBC_BXAP_RE_DISABLED    | \
 151                                         EBC_BXAP_SOR_DELAYED    | \
 152                                         EBC_BXAP_BEM_RW         | \
 153                                         EBC_BXAP_PEN_DISABLED
 154
 155 #define EBC_BXCR_FPGA_CS1               EBC_BXCR_BAS_ENCODE(0xe2000000) | \
 156                                         EBC_BXCR_BS_1MB                 | \
 157                                         EBC_BXCR_BU_RW                  | \
 158                                         EBC_BXCR_BW_16BIT
 159
 160          unsigned long mfr;
 161         /*
 162          * Define Variables for EBC initialization depending on BOOTSTRAP option
 163          */
 164         unsigned long sdr0_pinstp, sdr0_sdstp1 ;
 165         unsigned long bootstrap_settings, ebc_data_width, boot_selection;
 166         int computed_boot_device = BOOT_DEVICE_UNKNOWN;
 167
 168         /*-------------------------------------------------------------------+
 169          | Initialize EBC CONFIG -
 170          | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
 171          | default value :
 172          |      0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
 173          |
 174          +-------------------------------------------------------------------*/
 175         mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
 176                         EBC_CFG_PTD_ENABLE |
 177                         EBC_CFG_RTC_16PERCLK |
 178                         EBC_CFG_ATC_PREVIOUS |
 179                         EBC_CFG_DTC_PREVIOUS |
 180                         EBC_CFG_CTC_PREVIOUS |
 181                         EBC_CFG_OEO_PREVIOUS |
 182                         EBC_CFG_EMC_DEFAULT |
 183                         EBC_CFG_PME_DISABLE |
 184                         EBC_CFG_PR_16);
 185
 186         /*-------------------------------------------------------------------+
 187          |
 188          |  PART 1 : Initialize EBC Bank 1
 189          |  ==============================
 190          | Bank1 is always associated to the EPLD.
 191          | It has to be initialized prior to other banks settings computation
 192          | since some board registers values may be needed to determine the
 193          | boot type
 194          |
 195          +-------------------------------------------------------------------*/
 196         mtebc(pb1ap, EBC_BXAP_FPGA);
 197         mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
 198
 199         /*-------------------------------------------------------------------+
 200          |
 201          |  PART 2 : Determine which boot device was selected
 202          |  =================================================
 203          |
 204          |  Read Pin Strap Register in PPC440SPe
 205          |  Result can either be :
 206          |   - Boot strap = boot from EBC 8bits     => Small Flash
 207          |   - Boot strap = boot from PCI
 208          |   - Boot strap = IIC
 209          |  In case of boot from IIC, read Serial Device Strap Register1
 210          |
 211          |  Result can either be :
 212          |   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash
 213          |   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM
 214          |   - Boot from PCI
 215          |
 216          +-------------------------------------------------------------------*/
 217         /* Read Pin Strap Register in PPC440SP */
 218         mfsdr(SDR0_PINSTP, sdr0_pinstp);
 219         bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
 220
 221         switch (bootstrap_settings) {
 222                 case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
 223                         /*
 224                          * Strapping Option A
 225                          * Boot from EBC - 8 bits , Small Flash
 226                          */
 227                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 228                         break;
 229                 case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
 230                         /*
 231                          * Strappping Option B
 232                          * Boot from PCI
 233                          */
 234                         computed_boot_device = BOOT_FROM_PCI;
 235                         break;
 236                 case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
 237                 case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
 238                         /*
 239                          * Strapping Option C or D
 240                          * Boot Settings in IIC EEprom address 0x50 or 0x54
 241                          * Read Serial Device Strap Register1 in PPC440SPe
 242                          */
 243                         mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
 244                         boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
 245                         ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
 246
 247                         switch (boot_selection) {
 248                                 case SDR0_SDSTP1_ERPN_EBC:
 249                                         switch (ebc_data_width) {
 250                                                 case SDR0_SDSTP1_EBCW_16_BITS:
 251                                                         computed_boot_device =
 252                                                                 BOOT_FROM_LARGE_FLASH_OR_SRAM;
 253                                                         break;
 254                                                 case SDR0_SDSTP1_EBCW_8_BITS :
 255                                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 256                                                         break;
 257                                         }
 258                                         break;
 259
 260                                 case SDR0_SDSTP1_ERPN_PCI:
 261                                         computed_boot_device = BOOT_FROM_PCI;
 262                                         break;
 263                                 default:
 264                                         /* should not occure */
 265                                         computed_boot_device = BOOT_DEVICE_UNKNOWN;
 266                         }
 267                         break;
 268                 default:
 269                         /* should not be */
 270                         computed_boot_device = BOOT_DEVICE_UNKNOWN;
 271                         break;
 272         }
 273
 274         /*-------------------------------------------------------------------+
 275          |
 276          |  PART 3 : Compute EBC settings depending on selected boot device
 277          |  ======   ======================================================
 278          |
 279          | Resulting EBC init will be among following configurations :
 280          |
 281          |  - Boot from EBC 8bits => boot from Small Flash selected
 282          |            EBC-CS0     = Small Flash
 283          |            EBC-CS2     = Large Flash and SRAM
 284          |
 285          |  - Boot from EBC 16bits => boot from Large Flash or SRAM
 286          |            EBC-CS0     = Large Flash or SRAM
 287          |            EBC-CS2     = Small Flash
 288          |
 289          |  - Boot from PCI
 290          |            EBC-CS0     = not initialized to avoid address contention
 291          |            EBC-CS2     = same as boot from Small Flash selected
 292          |
 293          +-------------------------------------------------------------------*/
 294         unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
 295         unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
 296
 297         switch (computed_boot_device) {
 298                 /*-------------------------------------------------------------------*/
 299                 case BOOT_FROM_PCI:
 300                 /*-------------------------------------------------------------------*/
 301                         /*
 302                          * By Default CS2 is affected to LARGE Flash
 303                          * do not initialize SMALL FLASH to avoid address contention
 304                          * Large Flash
 305                          */
 306                         ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
 307                         ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
 308                         break;
 309
 310                 /*-------------------------------------------------------------------*/
 311                 case BOOT_FROM_SMALL_FLASH:
 312                 /*-------------------------------------------------------------------*/
 313                         ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
 314                         ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
 315
 316                         /*
 317                          * Large Flash or SRAM
 318                          */
 319                         /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
 320                         ebc0_cs2_bxap_value = 0x048ff240;
 321                         ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
 322                         break;
 323
 324                 /*-------------------------------------------------------------------*/
 325                 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
 326                 /*-------------------------------------------------------------------*/
 327                         ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
 328                         ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
 329
 330                         /* Small flash */
 331                         ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
 332                         ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
 333                         break;
 334
 335                 /*-------------------------------------------------------------------*/
 336                 default:
 337                 /*-------------------------------------------------------------------*/
 338                         /* BOOT_DEVICE_UNKNOWN */
 339                         break;
 340         }
 341
 342         mtebc(pb0ap, ebc0_cs0_bxap_value);
 343         mtebc(pb0cr, ebc0_cs0_bxcr_value);
 344         mtebc(pb2ap, ebc0_cs2_bxap_value);
 345         mtebc(pb2cr, ebc0_cs2_bxcr_value);
 346
 347         /*--------------------------------------------------------------------+
 348          | Interrupt controller setup for the AMCC 440SPe Evaluation board.
 349          +--------------------------------------------------------------------+
 350         +---------------------------------------------------------------------+
 351         |Interrupt| Source                            | Pol.  | Sensi.| Crit. |
 352         +---------+-----------------------------------+-------+-------+-------+
 353         | IRQ 00  | UART0                             | High  | Level | Non   |
 354         | IRQ 01  | UART1                             | High  | Level | Non   |
 355         | IRQ 02  | IIC0                              | High  | Level | Non   |
 356         | IRQ 03  | IIC1                              | High  | Level | Non   |
 357         | IRQ 04  | PCI0X0 MSG IN                     | High  | Level | Non   |
 358         | IRQ 05  | PCI0X0 CMD Write                  | High  | Level | Non   |
 359         | IRQ 06  | PCI0X0 Power Mgt                  | High  | Level | Non   |
 360         | IRQ 07  | PCI0X0 VPD Access                 | Rising| Edge  | Non   |
 361         | IRQ 08  | PCI0X0 MSI level 0                | High  | Lvl/ed| Non   |
 362         | IRQ 09  | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non   |
 363         | IRQ 10  | UIC2 Non-critical Int.            | NA    | NA    | Non   |
 364         | IRQ 11  | UIC2 Critical Interrupt           | NA    | NA    | Crit  |
 365         | IRQ 12  | PCI Express MSI Level 0           | Rising| Edge  | Non   |
 366         | IRQ 13  | PCI Express MSI Level 1           | Rising| Edge  | Non   |
 367         | IRQ 14  | PCI Express MSI Level 2           | Rising| Edge  | Non   |
 368         | IRQ 15  | PCI Express MSI Level 3           | Rising| Edge  | Non   |
 369         | IRQ 16  | UIC3 Non-critical Int.            | NA    | NA    | Non   |
 370         | IRQ 17  | UIC3 Critical Interrupt           | NA    | NA    | Crit  |
 371         | IRQ 18  | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non   |
 372         | IRQ 19  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
 373         | IRQ 20  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
 374         | IRQ 21  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
 375         | IRQ 22  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
 376         | IRQ 23  | I2O Inbound Doorbell              | High  | Level | Non   |
 377         | IRQ 24  | Inbound Post List FIFO Not Empt   | High  | Level | Non   |
 378         | IRQ 25  | I2O Region 0 LL PLB Write         | High  | Level | Non   |
 379         | IRQ 26  | I2O Region 1 LL PLB Write         | High  | Level | Non   |
 380         | IRQ 27  | I2O Region 0 HB PLB Write         | High  | Level | Non   |
 381         | IRQ 28  | I2O Region 1 HB PLB Write         | High  | Level | Non   |
 382         | IRQ 29  | GPT Down Count Timer              | Rising| Edge  | Non   |
 383         | IRQ 30  | UIC1 Non-critical Int.            | NA    | NA    | Non   |
 384         | IRQ 31  | UIC1 Critical Interrupt           | NA    | NA    | Crit. |
 385         |----------------------------------------------------------------------
 386         | IRQ 32  | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non   |
 387         | IRQ 33  | MAL Serr                          | High  | Level | Non   |
 388         | IRQ 34  | MAL Txde                          | High  | Level | Non   |
 389         | IRQ 35  | MAL Rxde                          | High  | Level | Non   |
 390         | IRQ 36  | DMC CE or DMC UE                  | High  | Level | Non   |
 391         | IRQ 37  | EBC or UART2                      | High  |Lvl Edg| Non   |
 392         | IRQ 38  | MAL TX EOB                        | High  | Level | Non   |
 393         | IRQ 39  | MAL RX EOB                        | High  | Level | Non   |
 394         | IRQ 40  | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non   |
 395         | IRQ 41  | PCIX0 MSI level 2                 | High  |Lvl Edg| Non   |
 396         | IRQ 42  | PCIX0 MSI level 3                 | High  |Lvl Edg| Non   |
 397         | IRQ 43  | L2 Cache                          | Risin | Edge  | Non   |
 398         | IRQ 44  | GPT Compare Timer 0               | Risin | Edge  | Non   |
 399         | IRQ 45  | GPT Compare Timer 1               | Risin | Edge  | Non   |
 400         | IRQ 46  | GPT Compare Timer 2               | Risin | Edge  | Non   |
 401         | IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
 402         | IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
 403         | IRQ 49  | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non   |
 404         | IRQ 50  | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non   |
 405         | IRQ 51  | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non   |
 406         | IRQ 52  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
 407         | IRQ 53  | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non   |
 408         | IRQ 54  | DMA Error                         | High  | Level | Non   |
 409         | IRQ 55  | DMA I2O Error                     | High  | Level | Non   |
 410         | IRQ 56  | Serial ROM                        | High  | Level | Non   |
 411         | IRQ 57  | PCIX0 Error                       | High  | Edge  | Non   |
 412         | IRQ 58  | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non   |
 413         | IRQ 59  | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non   |
 414         | IRQ 60  | EMAC0 Interrupt                   | High  | Level | Non   |
 415         | IRQ 61  | EMAC0 Wake-up                     | High  | Level | Non   |
 416         | IRQ 62  | Reserved                          | High  | Level | Non   |
 417         | IRQ 63  | XOR                               | High  | Level | Non   |
 418         |----------------------------------------------------------------------
 419         | IRQ 64  | PE0 AL                            | High  | Level | Non   |
 420         | IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
 421         | IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
 422         | IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
 423         | IRQ 68  | PE0 TCR                           | High  | Level | Non   |
 424         | IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
 425         | IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
 426         | IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
 427         | IRQ 72  | PE1 AL                            | High  | Level | Non   |
 428         | IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
 429         | IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
 430         | IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
 431         | IRQ 76  | PE1 TCR                           | High  | Level | Non   |
 432         | IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
 433         | IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
 434         | IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
 435         | IRQ 80  | PE2 AL                            | High  | Level | Non   |
 436         | IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
 437         | IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
 438         | IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
 439         | IRQ 84  | PE2 TCR                           | High  | Level | Non   |
 440         | IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
 441         | IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
 442         | IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
 443         | IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
 444         | IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
 445         | IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
 446         | IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
 447         | IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
 448         | IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
 449         | IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
 450         | IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
 451         |---------------------------------------------------------------------
 452         | IRQ 96  | PE0 INTA                          | High  | Level | Non   |
 453         | IRQ 97  | PE0 INTB                          | High  | Level | Non   |
 454         | IRQ 98  | PE0 INTC                          | High  | Level | Non   |
 455         | IRQ 99  | PE0 INTD                          | High  | Level | Non   |
 456         | IRQ 100 | PE1 INTA                          | High  | Level | Non   |
 457         | IRQ 101 | PE1 INTB                          | High  | Level | Non   |
 458         | IRQ 102 | PE1 INTC                          | High  | Level | Non   |
 459         | IRQ 103 | PE1 INTD                          | High  | Level | Non   |
 460         | IRQ 104 | PE2 INTA                          | High  | Level | Non   |
 461         | IRQ 105 | PE2 INTB                          | High  | Level | Non   |
 462         | IRQ 106 | PE2 INTC                          | High  | Level | Non   |
 463         | IRQ 107 | PE2 INTD                          | Risin | Edge  | Non   |
 464         | IRQ 108 | PCI Express MSI Level 4           | Risin | Edge  | Non   |
 465         | IRQ 109 | PCI Express MSI Level 5           | Risin | Edge  | Non   |
 466         | IRQ 110 | PCI Express MSI Level 6           | Risin | Edge  | Non   |
 467         | IRQ 111 | PCI Express MSI Level 7           | Risin | Edge  | Non   |
 468         | IRQ 116 | PCI Express MSI Level 12          | Risin | Edge  | Non   |
 469         | IRQ 112 | PCI Express MSI Level 8           | Risin | Edge  | Non   |
 470         | IRQ 113 | PCI Express MSI Level 9           | Risin | Edge  | Non   |
 471         | IRQ 114 | PCI Express MSI Level 10          | Risin | Edge  | Non   |
 472         | IRQ 115 | PCI Express MSI Level 11          | Risin | Edge  | Non   |
 473         | IRQ 117 | PCI Express MSI Level 13          | Risin | Edge  | Non   |
 474         | IRQ 118 | PCI Express MSI Level 14          | Risin | Edge  | Non   |
 475         | IRQ 119 | PCI Express MSI Level 15          | Risin | Edge  | Non   |
 476         | IRQ 120 | PCI Express MSI Level 16          | Risin | Edge  | Non   |
 477         | IRQ 121 | PCI Express MSI Level 17          | Risin | Edge  | Non   |
 478         | IRQ 122 | PCI Express MSI Level 18          | Risin | Edge  | Non   |
 479         | IRQ 123 | PCI Express MSI Level 19          | Risin | Edge  | Non   |
 480         | IRQ 124 | PCI Express MSI Level 20          | Risin | Edge  | Non   |
 481         | IRQ 125 | PCI Express MSI Level 21          | Risin | Edge  | Non   |
 482         | IRQ 126 | PCI Express MSI Level 22          | Risin | Edge  | Non   |
 483         | IRQ 127 | PCI Express MSI Level 23          | Risin | Edge  | Non   |
 484         +---------+-----------------------------------+-------+-------+------*/
 485         /*--------------------------------------------------------------------+
 486          | Put UICs in PowerPC440SPemode.
 487          | Initialise UIC registers.  Clear all interrupts.  Disable all
 488          | interrupts.
 489          | Set critical interrupt values.  Set interrupt polarities.  Set
 490          | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
 491          | interrupts again.
 492          +-------------------------------------------------------------------*/
 493         mtdcr (uic3sr, 0xffffffff);     /* Clear all interrupts */
 494         mtdcr (uic3er, 0x00000000);     /* disable all interrupts */
 495         mtdcr (uic3cr, 0x00000000);     /* Set Critical / Non Critical
 496                                          * interrupts */
 497         mtdcr (uic3pr, 0xffffffff);     /* Set Interrupt Polarities */
 498         mtdcr (uic3tr, 0x001fffff);     /* Set Interrupt Trigger Levels */
 499         mtdcr (uic3vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
 500                                          * priority */
 501         mtdcr (uic3sr, 0x00000000);     /* clear all  interrupts */
 502         mtdcr (uic3sr, 0xffffffff);     /* clear all  interrupts */
 503
 504         mtdcr (uic2sr, 0xffffffff);     /* Clear all interrupts */
 505         mtdcr (uic2er, 0x00000000);     /* disable all interrupts */
 506         mtdcr (uic2cr, 0x00000000);     /* Set Critical / Non Critical
 507                                          * interrupts */
 508         mtdcr (uic2pr, 0xebebebff);     /* Set Interrupt Polarities */
 509         mtdcr (uic2tr, 0x74747400);     /* Set Interrupt Trigger Levels */
 510         mtdcr (uic2vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
 511                                          * priority */
 512         mtdcr (uic2sr, 0x00000000);     /* clear all interrupts */
 513         mtdcr (uic2sr, 0xffffffff);     /* clear all interrupts */
 514
 515         mtdcr (uic1sr, 0xffffffff);     /* Clear all interrupts */
 516         mtdcr (uic1er, 0x00000000);     /* disable all interrupts */
 517         mtdcr (uic1cr, 0x00000000);     /* Set Critical / Non Critical
 518                                          * interrupts */
 519         mtdcr (uic1pr, 0xffffffff);     /* Set Interrupt Polarities */
 520         mtdcr (uic1tr, 0x001f8040);     /* Set Interrupt Trigger Levels */
 521         mtdcr (uic1vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
 522                                          * priority */
 523         mtdcr (uic1sr, 0x00000000);     /* clear all interrupts */
 524         mtdcr (uic1sr, 0xffffffff);     /* clear all interrupts */
 525
 526         mtdcr (uic0sr, 0xffffffff);     /* Clear all interrupts */
 527         mtdcr (uic0er, 0x00000000);     /* disable all interrupts excepted
 528                                          * cascade to be checked */
 529         mtdcr (uic0cr, 0x00104001);     /* Set Critical / Non Critical
 530                                          * interrupts */
 531         mtdcr (uic0pr, 0xffffffff);     /* Set Interrupt Polarities */
 532         mtdcr (uic0tr, 0x010f0004);     /* Set Interrupt Trigger Levels */
 533         mtdcr (uic0vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
 534                                          * priority */
 535         mtdcr (uic0sr, 0x00000000);     /* clear all interrupts */
 536         mtdcr (uic0sr, 0xffffffff);     /* clear all interrupts */
 537
 538         /* SDR0_MFR should be part of Ethernet init */
 539         mfsdr (sdr_mfr, mfr);
 540         mfr &= ~SDR0_MFR_ECS_MASK;
 541         /*mtsdr(sdr_mfr, mfr);*/
 542         fpga_init();
 543
 544         return 0;
 545 }
 546
 547 int checkboard (void)
 548 {
 549         char *s = getenv("serial#");
 550
 551         printf("Board: Yucca - AMCC 440SPe Evaluation Board");
 552         if (s != NULL) {
 553                 puts(", serial# ");
 554                 puts(s);
 555         }
 556         putc('\n');
 557
 558         return 0;
 559 }
 560
 561 /*
 562  * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
 563  * board specific values.
 564  */
 565 static int ppc440spe_rev_a(void)
 566 {
 567         if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
 568                 return 1;
 569         else
 570                 return 0;
 571 }
 572
 573 u32 ddr_wrdtr(u32 default_val) {
 574         /*
 575          * Yucca boards with 440SPe rev. A need a slightly different setup
 576          * for the MCIF0_WRDTR register.
 577          */
 578         if (ppc440spe_rev_a())
 579                 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
 580
 581         return default_val;
 582 }
 583
 584 u32 ddr_clktr(u32 default_val) {
 585         /*
 586          * Yucca boards with 440SPe rev. A need a slightly different setup
 587          * for the MCIF0_CLKTR register.
 588          */
 589         if (ppc440spe_rev_a())
 590                 return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
 591
 592         return default_val;
 593 }
 594
 595 #if defined(CFG_DRAM_TEST)
 596 int testdram (void)
 597 {
 598         uint *pstart = (uint *) 0x00000000;
 599         uint *pend = (uint *) 0x08000000;
 600         uint *p;
 601
 602         for (p = pstart; p < pend; p++)
 603                 *p = 0xaaaaaaaa;
 604
 605         for (p = pstart; p < pend; p++) {
 606                 if (*p != 0xaaaaaaaa) {
 607                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 608                         return 1;
 609                 }
 610         }
 611
 612         for (p = pstart; p < pend; p++)
 613                 *p = 0x55555555;
 614
 615         for (p = pstart; p < pend; p++) {
 616                 if (*p != 0x55555555) {
 617                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 618                         return 1;
 619                 }
 620         }
 621         return 0;
 622 }
 623 #endif
 624
 625 /*************************************************************************
 626  *  pci_pre_init
 627  *
 628  *  This routine is called just prior to registering the hose and gives
 629  *  the board the opportunity to check things. Returning a value of zero
 630  *  indicates that things are bad & PCI initialization should be aborted.
 631  *
 632  *      Different boards may wish to customize the pci controller structure
 633  *      (add regions, override default access routines, etc) or perform
 634  *      certain pre-initialization actions.
 635  *
 636  ************************************************************************/
 637 #if defined(CONFIG_PCI)
 638 int pci_pre_init(struct pci_controller * hose )
 639 {
 640         unsigned long strap;
 641
 642         /*-------------------------------------------------------------------+
 643          *      The yucca board is always configured as the host & requires the
 644          *      PCI arbiter to be enabled.
 645          *-------------------------------------------------------------------*/
 646         mfsdr(sdr_sdstp1, strap);
 647         if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
 648                 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
 649                 return 0;
 650         }
 651
 652         return 1;
 653 }
 654 #endif  /* defined(CONFIG_PCI) */
 655
 656 /*************************************************************************
 657  *  pci_target_init
 658  *
 659  *      The bootstrap configuration provides default settings for the pci
 660  *      inbound map (PIM). But the bootstrap config choices are limited and
 661  *      may not be sufficient for a given board.
 662  *
 663  ************************************************************************/
 664 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 665 void pci_target_init(struct pci_controller * hose )
 666 {
 667         /*-------------------------------------------------------------------+
 668          * Disable everything
 669          *-------------------------------------------------------------------*/
 670         out32r( PCIX0_PIM0SA, 0 ); /* disable */
 671         out32r( PCIX0_PIM1SA, 0 ); /* disable */
 672         out32r( PCIX0_PIM2SA, 0 ); /* disable */
 673         out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
 674
 675         /*-------------------------------------------------------------------+
 676          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 677          * strapping options to not support sizes such as 128/256 MB.
 678          *-------------------------------------------------------------------*/
 679         out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
 680         out32r( PCIX0_PIM0LAH, 0 );
 681         out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 682         out32r( PCIX0_BAR0, 0 );
 683
 684         /*-------------------------------------------------------------------+
 685          * Program the board's subsystem id/vendor id
 686          *-------------------------------------------------------------------*/
 687         out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
 688         out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
 689
 690         out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 691 }
 692 #endif  /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 693
 694 #if defined(CONFIG_PCI)
 695 /*************************************************************************
 696  *  is_pci_host
 697  *
 698  *      This routine is called to determine if a pci scan should be
 699  *      performed. With various hardware environments (especially cPCI and
 700  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 701  *      bit in the strap register, or generic host/adapter assumptions.
 702  *
 703  *      Rather than hard-code a bad assumption in the general 440 code, the
 704  *      440 pci code requires the board to decide at runtime.
 705  *
 706  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 707  *
 708  *
 709  ************************************************************************/
 710 int is_pci_host(struct pci_controller *hose)
 711 {
 712         /* The yucca board is always configured as host. */
 713         return 1;
 714 }
 715
 716 int yucca_pcie_card_present(int port)
 717 {
 718         u16 reg;
 719
 720         reg = in_be16((u16 *)FPGA_REG1C);
 721         switch(port) {
 722         case 0:
 723                 return !(reg & FPGA_REG1C_PE0_PRSNT);
 724         case 1:
 725                 return !(reg & FPGA_REG1C_PE1_PRSNT);
 726         case 2:
 727                 return !(reg & FPGA_REG1C_PE2_PRSNT);
 728         default:
 729                 return 0;
 730         }
 731 }
 732
 733 /*
 734  * For the given slot, set rootpoint mode, send power to the slot,
 735  * turn on the green LED and turn off the yellow LED, enable the clock
 736  * and turn off reset.
 737  */
 738 void yucca_setup_pcie_fpga_rootpoint(int port)
 739 {
 740         u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
 741
 742         switch(port) {
 743         case 0:
 744                 rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
 745                 endpoint    = 0;
 746                 power       = FPGA_REG1A_PE0_PWRON;
 747                 green_led   = FPGA_REG1A_PE0_GLED;
 748                 clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
 749                 yellow_led  = FPGA_REG1A_PE0_YLED;
 750                 reset_off   = FPGA_REG1C_PE0_PERST;
 751                 break;
 752         case 1:
 753                 rootpoint   = 0;
 754                 endpoint    = FPGA_REG1C_PE1_ENDPOINT;
 755                 power       = FPGA_REG1A_PE1_PWRON;
 756                 green_led   = FPGA_REG1A_PE1_GLED;
 757                 clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
 758                 yellow_led  = FPGA_REG1A_PE1_YLED;
 759                 reset_off   = FPGA_REG1C_PE1_PERST;
 760                 break;
 761         case 2:
 762                 rootpoint   = 0;
 763                 endpoint    = FPGA_REG1C_PE2_ENDPOINT;
 764                 power       = FPGA_REG1A_PE2_PWRON;
 765                 green_led   = FPGA_REG1A_PE2_GLED;
 766                 clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
 767                 yellow_led  = FPGA_REG1A_PE2_YLED;
 768                 reset_off   = FPGA_REG1C_PE2_PERST;
 769                 break;
 770
 771         default:
 772                 return;
 773         }
 774
 775         out_be16((u16 *)FPGA_REG1A,
 776                  ~(power | clock | green_led) &
 777                  (yellow_led | in_be16((u16 *)FPGA_REG1A)));
 778
 779         out_be16((u16 *)FPGA_REG1C,
 780                  ~(endpoint | reset_off) &
 781                  (rootpoint | in_be16((u16 *)FPGA_REG1C)));
 782         /*
 783          * Leave device in reset for a while after powering on the
 784          * slot to give it a chance to initialize.
 785          */
 786         udelay(250 * 1000);
 787
 788         out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C));
 789 }
 790 /*
 791  * For the given slot, set endpoint mode, send power to the slot,
 792  * turn on the green LED and turn off the yellow LED, enable the clock
 793  * .In end point mode reset bit is  read only.
 794  */
 795 void yucca_setup_pcie_fpga_endpoint(int port)
 796 {
 797         u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
 798
 799         switch(port) {
 800         case 0:
 801                 rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
 802                 endpoint    = 0;
 803                 power       = FPGA_REG1A_PE0_PWRON;
 804                 green_led   = FPGA_REG1A_PE0_GLED;
 805                 clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
 806                 yellow_led  = FPGA_REG1A_PE0_YLED;
 807                 reset_off   = FPGA_REG1C_PE0_PERST;
 808                 break;
 809         case 1:
 810                 rootpoint   = 0;
 811                 endpoint    = FPGA_REG1C_PE1_ENDPOINT;
 812                 power       = FPGA_REG1A_PE1_PWRON;
 813                 green_led   = FPGA_REG1A_PE1_GLED;
 814                 clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
 815                 yellow_led  = FPGA_REG1A_PE1_YLED;
 816                 reset_off   = FPGA_REG1C_PE1_PERST;
 817                 break;
 818         case 2:
 819                 rootpoint   = 0;
 820                 endpoint    = FPGA_REG1C_PE2_ENDPOINT;
 821                 power       = FPGA_REG1A_PE2_PWRON;
 822                 green_led   = FPGA_REG1A_PE2_GLED;
 823                 clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
 824                 yellow_led  = FPGA_REG1A_PE2_YLED;
 825                 reset_off   = FPGA_REG1C_PE2_PERST;
 826                 break;
 827
 828         default:
 829                 return;
 830         }
 831
 832         out_be16((u16 *)FPGA_REG1A,
 833                  ~(power | clock | green_led) &
 834                  (yellow_led | in_be16((u16 *)FPGA_REG1A)));
 835
 836         out_be16((u16 *)FPGA_REG1C,
 837                  ~(rootpoint | reset_off) &
 838                  (endpoint | in_be16((u16 *)FPGA_REG1C)));
 839 }
 840
 841 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
 842
 843 void pcie_setup_hoses(int busno)
 844 {
 845         struct pci_controller *hose;
 846         int i, bus;
 847         int ret = 0;
 848         char *env;
 849         unsigned int delay;
 850
 851         /*
 852          * assume we're called after the PCIX hose is initialized, which takes
 853          * bus ID 0 and therefore start numbering PCIe's from 1.
 854          */
 855         bus = busno;
 856         for (i = 0; i <= 2; i++) {
 857                 /* Check for yucca card presence */
 858                 if (!yucca_pcie_card_present(i))
 859                         continue;
 860
 861                 if (is_end_point(i)) {
 862                         printf("PCIE%d: will be configured as endpoint\n",i);
 863                         yucca_setup_pcie_fpga_endpoint(i);
 864                         ret = ppc4xx_init_pcie_endport(i);
 865                 } else {
 866                         printf("PCIE%d: will be configured as root-complex\n",i);
 867                         yucca_setup_pcie_fpga_rootpoint(i);
 868                         ret = ppc4xx_init_pcie_rootport(i);
 869                 }
 870                 if (ret) {
 871                         printf("PCIE%d: initialization failed\n", i);
 872                         continue;
 873                 }
 874
 875                 hose = &pcie_hose[i];
 876                 hose->first_busno = bus;
 877                 hose->last_busno = bus;
 878                 hose->current_busno = bus;
 879
 880                 /* setup mem resource */
 881                 pci_set_region(hose->regions + 0,
 882                         CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
 883                         CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
 884                         CFG_PCIE_MEMSIZE,
 885                         PCI_REGION_MEM);
 886                 hose->region_count = 1;
 887                 pci_register_hose(hose);
 888
 889                 if (is_end_point(i)) {
 890                         ppc4xx_setup_pcie_endpoint(hose, i);
 891                         /*
 892                          * Reson for no scanning is endpoint can not generate
 893                          * upstream configuration accesses.
 894                          */
 895                 } else {
 896                         ppc4xx_setup_pcie_rootpoint(hose, i);
 897                         env = getenv("pciscandelay");
 898                         if (env != NULL) {
 899                                 delay = simple_strtoul(env, NULL, 10);
 900                                 if (delay > 5)
 901                                         printf("Warning, expect noticable delay before "
 902                                                "PCIe scan due to 'pciscandelay' value!\n");
 903                                 mdelay(delay * 1000);
 904                         }
 905
 906                         /*
 907                          * Config access can only go down stream
 908                          */
 909                         hose->last_busno = pci_hose_scan(hose);
 910                         bus = hose->last_busno + 1;
 911                 }
 912         }
 913 }
 914 #endif  /* defined(CONFIG_PCI) */
 915
 916 int misc_init_f (void)
 917 {
 918         uint reg;
 919 #if defined(CONFIG_STRESS)
 920         uint i ;
 921         uint disp;
 922 #endif
 923
 924         out16(FPGA_REG10, (in16(FPGA_REG10) &
 925                         ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
 926                                 FPGA_REG10_10MHZ_ENABLE |
 927                                 FPGA_REG10_100MHZ_ENABLE |
 928                                 FPGA_REG10_GIGABIT_ENABLE |
 929                                 FPGA_REG10_FULL_DUPLEX );
 930
 931         udelay(10000);  /* wait 10ms */
 932
 933         out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
 934
 935         /* minimal init for PCIe */
 936         /* pci express 0 Endpoint Mode */
 937         mfsdr(SDR0_PE0DLPSET, reg);
 938         reg &= (~0x00400000);
 939         mtsdr(SDR0_PE0DLPSET, reg);
 940         /* pci express 1 Rootpoint  Mode */
 941         mfsdr(SDR0_PE1DLPSET, reg);
 942         reg |= 0x00400000;
 943         mtsdr(SDR0_PE1DLPSET, reg);
 944         /* pci express 2 Rootpoint  Mode */
 945         mfsdr(SDR0_PE2DLPSET, reg);
 946         reg |= 0x00400000;
 947         mtsdr(SDR0_PE2DLPSET, reg);
 948
 949         out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
 950                                 ~FPGA_REG1C_PE0_ROOTPOINT &
 951                                 ~FPGA_REG1C_PE1_ENDPOINT  &
 952                                 ~FPGA_REG1C_PE2_ENDPOINT));
 953
 954 #if defined(CONFIG_STRESS)
 955         /*
 956          * all this setting done by linux only needed by stress an charac. test
 957          * procedure
 958          * PCIe 1 Rootpoint PCIe2 Endpoint
 959          * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
 960          * Power Level
 961          */
 962         for (i = 0, disp = 0; i < 8; i++, disp += 3) {
 963                 mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
 964                 reg |= 0x33000000;
 965                 mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
 966         }
 967
 968         /*
 969          * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
 970          * Power Level
 971          */
 972         for (i = 0, disp = 0; i < 4; i++, disp += 3) {
 973                 mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
 974                 reg |= 0x33000000;
 975                 mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
 976         }
 977
 978         /*
 979          * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
 980          * Power Level
 981          */
 982         for (i = 0, disp = 0; i < 4; i++, disp += 3) {
 983                 mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
 984                 reg |= 0x33000000;
 985                 mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
 986         }
 987
 988         reg = 0x21242222;
 989         mtsdr(SDR0_PE2UTLSET1, reg);
 990         reg = 0x11000000;
 991         mtsdr(SDR0_PE2UTLSET2, reg);
 992         /* pci express 1 Endpoint  Mode */
 993         reg = 0x00004000;
 994         mtsdr(SDR0_PE2DLPSET, reg);
 995
 996         mtsdr(SDR0_UART1, 0x2080005a);  /* patch for TG */
 997 #endif
 998         return 0;
 999 }
1000
1001 void fpga_init(void)
1002 {
1003         /*
1004          * by default sdram access is disabled by fpga
1005          */
1006         out16(FPGA_REG10, (in16 (FPGA_REG10) |
1007                                 FPGA_REG10_SDRAM_ENABLE |
1008                                 FPGA_REG10_ENABLE_DISPLAY ));
1009
1010         return;
1011 }
1012
1013 #ifdef CONFIG_POST
1014 /*
1015  * Returns 1 if keys pressed to start the power-on long-running tests
1016  * Called from board_init_f().
1017  */
1018 int post_hotkeys_pressed(void)
1019 {
1020         return (ctrlc());
1021 }
1022 #endif
1023
1024 /*---------------------------------------------------------------------------+
1025  | onboard_pci_arbiter_selected => from EPLD
1026  +---------------------------------------------------------------------------*/
1027 int onboard_pci_arbiter_selected(int core_pci)
1028 {
1029 #if 0
1030         unsigned long onboard_pci_arbiter_sel;
1031
1032         onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
1033
1034         if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
1035                 return (BOARD_OPTION_SELECTED);
1036         else
1037 #endif
1038         return (BOARD_OPTION_NOT_SELECTED);
1039 }