board/amcc/yucca/yucca.c

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  * Port to AMCC-440SPE Evaluation Board SOP - April 2005
  24  *
  25  * PCIe supporting routines derived from Linux 440SPe PCIe driver.
  26  */
  27
  28 #include <common.h>
  29 #include <ppc4xx.h>
  30 #include <asm/processor.h>
  31 #include <i2c.h>
  32 #include <asm-ppc/io.h>
  33
  34 #include "yucca.h"
  35 #include "../cpu/ppc4xx/440spe_pcie.h"
  36
  37 #undef PCIE_ENDPOINT
  38 /* #define PCIE_ENDPOINT 1 */
  39
  40 void fpga_init (void);
  41
  42 void get_sys_info(PPC440_SYS_INFO *board_cfg );
  43 int compare_to_true(char *str );
  44 char *remove_l_w_space(char *in_str );
  45 char *remove_t_w_space(char *in_str );
  46 int get_console_port(void);
  47
  48 int ppc440spe_init_pcie_rootport(int port);
  49 void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
  50
  51 #define DEBUG_ENV
  52 #ifdef DEBUG_ENV
  53 #define DEBUGF(fmt,args...) printf(fmt ,##args)
  54 #else
  55 #define DEBUGF(fmt,args...)
  56 #endif
  57
  58 #define FALSE   0
  59 #define TRUE    1
  60
  61 int board_early_init_f (void)
  62 {
  63 /*----------------------------------------------------------------------------+
  64 | Define Boot devices
  65 +----------------------------------------------------------------------------*/
  66 #define BOOT_FROM_SMALL_FLASH           0x00
  67 #define BOOT_FROM_LARGE_FLASH_OR_SRAM   0x01
  68 #define BOOT_FROM_PCI                   0x02
  69 #define BOOT_DEVICE_UNKNOWN             0x03
  70
  71 /*----------------------------------------------------------------------------+
  72 | EBC Devices Characteristics
  73 |   Peripheral Bank Access Parameters       -   EBC_BxAP
  74 |   Peripheral Bank Configuration Register  -   EBC_BxCR
  75 +----------------------------------------------------------------------------*/
  76
  77 /*
  78  * Small Flash and FRAM
  79  * BU Value
  80  * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
  81  * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000
  82  * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000
  83  */
  84 #define EBC_BXAP_SMALL_FLASH            EBC_BXAP_BME_DISABLED   | \
  85                                         EBC_BXAP_TWT_ENCODE(7)  | \
  86                                         EBC_BXAP_BCE_DISABLE    | \
  87                                         EBC_BXAP_BCT_2TRANS     | \
  88                                         EBC_BXAP_CSN_ENCODE(0)  | \
  89                                         EBC_BXAP_OEN_ENCODE(0)  | \
  90                                         EBC_BXAP_WBN_ENCODE(0)  | \
  91                                         EBC_BXAP_WBF_ENCODE(0)  | \
  92                                         EBC_BXAP_TH_ENCODE(0)   | \
  93                                         EBC_BXAP_RE_DISABLED    | \
  94                                         EBC_BXAP_SOR_DELAYED    | \
  95                                         EBC_BXAP_BEM_WRITEONLY  | \
  96                                         EBC_BXAP_PEN_DISABLED
  97
  98 #define EBC_BXCR_SMALL_FLASH_CS0        EBC_BXCR_BAS_ENCODE(0xFF000000) | \
  99                                         EBC_BXCR_BS_16MB                | \
 100                                         EBC_BXCR_BU_RW                  | \
 101                                         EBC_BXCR_BW_8BIT
 102
 103 #define EBC_BXCR_SMALL_FLASH_CS2        EBC_BXCR_BAS_ENCODE(0xe7000000) | \
 104                                         EBC_BXCR_BS_16MB                | \
 105                                         EBC_BXCR_BU_RW                  | \
 106                                         EBC_BXCR_BW_8BIT
 107
 108 /*
 109  * Large Flash and SRAM
 110  * BU Value
 111  * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
 112  * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
 113  * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
 114 */
 115 #define EBC_BXAP_LARGE_FLASH            EBC_BXAP_BME_DISABLED   | \
 116                                         EBC_BXAP_TWT_ENCODE(7)  | \
 117                                         EBC_BXAP_BCE_DISABLE    | \
 118                                         EBC_BXAP_BCT_2TRANS     | \
 119                                         EBC_BXAP_CSN_ENCODE(0)  | \
 120                                         EBC_BXAP_OEN_ENCODE(0)  | \
 121                                         EBC_BXAP_WBN_ENCODE(0)  | \
 122                                         EBC_BXAP_WBF_ENCODE(0)  | \
 123                                         EBC_BXAP_TH_ENCODE(0)   | \
 124                                         EBC_BXAP_RE_DISABLED    | \
 125                                         EBC_BXAP_SOR_DELAYED    | \
 126                                         EBC_BXAP_BEM_WRITEONLY  | \
 127                                         EBC_BXAP_PEN_DISABLED
 128
 129 #define EBC_BXCR_LARGE_FLASH_CS0        EBC_BXCR_BAS_ENCODE(0xFF000000) | \
 130                                         EBC_BXCR_BS_16MB                | \
 131                                         EBC_BXCR_BU_RW                  | \
 132                                         EBC_BXCR_BW_16BIT
 133
 134 #define EBC_BXCR_LARGE_FLASH_CS2        EBC_BXCR_BAS_ENCODE(0xE7000000) | \
 135                                         EBC_BXCR_BS_16MB                | \
 136                                         EBC_BXCR_BU_RW                  | \
 137                                         EBC_BXCR_BW_16BIT
 138
 139 /*
 140  * FPGA
 141  * BU value :
 142  * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
 143  * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000
 144  */
 145 #define EBC_BXAP_FPGA                   EBC_BXAP_BME_DISABLED   | \
 146                                         EBC_BXAP_TWT_ENCODE(11) | \
 147                                         EBC_BXAP_BCE_DISABLE    | \
 148                                         EBC_BXAP_BCT_2TRANS     | \
 149                                         EBC_BXAP_CSN_ENCODE(10) | \
 150                                         EBC_BXAP_OEN_ENCODE(1)  | \
 151                                         EBC_BXAP_WBN_ENCODE(1)  | \
 152                                         EBC_BXAP_WBF_ENCODE(1)  | \
 153                                         EBC_BXAP_TH_ENCODE(1)   | \
 154                                         EBC_BXAP_RE_DISABLED    | \
 155                                         EBC_BXAP_SOR_DELAYED    | \
 156                                         EBC_BXAP_BEM_RW         | \
 157                                         EBC_BXAP_PEN_DISABLED
 158
 159 #define EBC_BXCR_FPGA_CS1               EBC_BXCR_BAS_ENCODE(0xe2000000) | \
 160                                         EBC_BXCR_BS_1MB                 | \
 161                                         EBC_BXCR_BU_RW                  | \
 162                                         EBC_BXCR_BW_16BIT
 163
 164          unsigned long mfr;
 165         /*
 166          * Define Variables for EBC initialization depending on BOOTSTRAP option
 167          */
 168         unsigned long sdr0_pinstp, sdr0_sdstp1 ;
 169         unsigned long bootstrap_settings, ebc_data_width, boot_selection;
 170         int computed_boot_device = BOOT_DEVICE_UNKNOWN;
 171
 172         /*-------------------------------------------------------------------+
 173          | Initialize EBC CONFIG -
 174          | Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
 175          | default value :
 176          |      0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
 177          |
 178          +-------------------------------------------------------------------*/
 179         mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
 180                         EBC_CFG_PTD_ENABLE |
 181                         EBC_CFG_RTC_16PERCLK |
 182                         EBC_CFG_ATC_PREVIOUS |
 183                         EBC_CFG_DTC_PREVIOUS |
 184                         EBC_CFG_CTC_PREVIOUS |
 185                         EBC_CFG_OEO_PREVIOUS |
 186                         EBC_CFG_EMC_DEFAULT |
 187                         EBC_CFG_PME_DISABLE |
 188                         EBC_CFG_PR_16);
 189
 190         /*-------------------------------------------------------------------+
 191          |
 192          |  PART 1 : Initialize EBC Bank 1
 193          |  ==============================
 194          | Bank1 is always associated to the EPLD.
 195          | It has to be initialized prior to other banks settings computation
 196          | since some board registers values may be needed to determine the
 197          | boot type
 198          |
 199          +-------------------------------------------------------------------*/
 200         mtebc(pb1ap, EBC_BXAP_FPGA);
 201         mtebc(pb1cr, EBC_BXCR_FPGA_CS1);
 202
 203         /*-------------------------------------------------------------------+
 204          |
 205          |  PART 2 : Determine which boot device was selected
 206          |  =================================================
 207          |
 208          |  Read Pin Strap Register in PPC440SPe
 209          |  Result can either be :
 210          |   - Boot strap = boot from EBC 8bits     => Small Flash
 211          |   - Boot strap = boot from PCI
 212          |   - Boot strap = IIC
 213          |  In case of boot from IIC, read Serial Device Strap Register1
 214          |
 215          |  Result can either be :
 216          |   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash
 217          |   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM
 218          |   - Boot from PCI
 219          |
 220          +-------------------------------------------------------------------*/
 221         /* Read Pin Strap Register in PPC440SP */
 222         mfsdr(SDR0_PINSTP, sdr0_pinstp);
 223         bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
 224
 225         switch (bootstrap_settings) {
 226                 case SDR0_PINSTP_BOOTSTRAP_SETTINGS0:
 227                         /*
 228                          * Strapping Option A
 229                          * Boot from EBC - 8 bits , Small Flash
 230                          */
 231                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 232                         break;
 233                 case SDR0_PINSTP_BOOTSTRAP_SETTINGS1:
 234                         /*
 235                          * Strappping Option B
 236                          * Boot from PCI
 237                          */
 238                         computed_boot_device = BOOT_FROM_PCI;
 239                         break;
 240                 case SDR0_PINSTP_BOOTSTRAP_IIC_50_EN:
 241                 case SDR0_PINSTP_BOOTSTRAP_IIC_54_EN:
 242                         /*
 243                          * Strapping Option C or D
 244                          * Boot Settings in IIC EEprom address 0x50 or 0x54
 245                          * Read Serial Device Strap Register1 in PPC440SPe
 246                          */
 247                         mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
 248                         boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
 249                         ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
 250
 251                         switch (boot_selection) {
 252                                 case SDR0_SDSTP1_ERPN_EBC:
 253                                         switch (ebc_data_width) {
 254                                                 case SDR0_SDSTP1_EBCW_16_BITS:
 255                                                         computed_boot_device =
 256                                                                 BOOT_FROM_LARGE_FLASH_OR_SRAM;
 257                                                         break;
 258                                                 case SDR0_SDSTP1_EBCW_8_BITS :
 259                                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 260                                                         break;
 261                                         }
 262                                         break;
 263
 264                                 case SDR0_SDSTP1_ERPN_PCI:
 265                                         computed_boot_device = BOOT_FROM_PCI;
 266                                         break;
 267                                 default:
 268                                         /* should not occure */
 269                                         computed_boot_device = BOOT_DEVICE_UNKNOWN;
 270                         }
 271                         break;
 272                 default:
 273                         /* should not be */
 274                         computed_boot_device = BOOT_DEVICE_UNKNOWN;
 275                         break;
 276         }
 277
 278         /*-------------------------------------------------------------------+
 279          |
 280          |  PART 3 : Compute EBC settings depending on selected boot device
 281          |  ======   ======================================================
 282          |
 283          | Resulting EBC init will be among following configurations :
 284          |
 285          |  - Boot from EBC 8bits => boot from Small Flash selected
 286          |            EBC-CS0     = Small Flash
 287          |            EBC-CS2     = Large Flash and SRAM
 288          |
 289          |  - Boot from EBC 16bits => boot from Large Flash or SRAM
 290          |            EBC-CS0     = Large Flash or SRAM
 291          |            EBC-CS2     = Small Flash
 292          |
 293          |  - Boot from PCI
 294          |            EBC-CS0     = not initialized to avoid address contention
 295          |            EBC-CS2     = same as boot from Small Flash selected
 296          |
 297          +-------------------------------------------------------------------*/
 298         unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
 299         unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
 300
 301         switch (computed_boot_device) {
 302                 /*-------------------------------------------------------------------*/
 303                 case BOOT_FROM_PCI:
 304                 /*-------------------------------------------------------------------*/
 305                         /*
 306                          * By Default CS2 is affected to LARGE Flash
 307                          * do not initialize SMALL FLASH to avoid address contention
 308                          * Large Flash
 309                          */
 310                         ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH;
 311                         ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
 312                         break;
 313
 314                 /*-------------------------------------------------------------------*/
 315                 case BOOT_FROM_SMALL_FLASH:
 316                 /*-------------------------------------------------------------------*/
 317                         ebc0_cs0_bxap_value = EBC_BXAP_SMALL_FLASH;
 318                         ebc0_cs0_bxcr_value = EBC_BXCR_SMALL_FLASH_CS0;
 319
 320                         /*
 321                          * Large Flash or SRAM
 322                          */
 323                         /* ebc0_cs2_bxap_value = EBC_BXAP_LARGE_FLASH; */
 324                         ebc0_cs2_bxap_value = 0x048ff240;
 325                         ebc0_cs2_bxcr_value = EBC_BXCR_LARGE_FLASH_CS2;
 326                         break;
 327
 328                 /*-------------------------------------------------------------------*/
 329                 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
 330                 /*-------------------------------------------------------------------*/
 331                         ebc0_cs0_bxap_value = EBC_BXAP_LARGE_FLASH;
 332                         ebc0_cs0_bxcr_value = EBC_BXCR_LARGE_FLASH_CS0;
 333
 334                         /* Small flash */
 335                         ebc0_cs2_bxap_value = EBC_BXAP_SMALL_FLASH;
 336                         ebc0_cs2_bxcr_value = EBC_BXCR_SMALL_FLASH_CS2;
 337                         break;
 338
 339                 /*-------------------------------------------------------------------*/
 340                 default:
 341                 /*-------------------------------------------------------------------*/
 342                         /* BOOT_DEVICE_UNKNOWN */
 343                         break;
 344         }
 345
 346         mtebc(pb0ap, ebc0_cs0_bxap_value);
 347         mtebc(pb0cr, ebc0_cs0_bxcr_value);
 348         mtebc(pb2ap, ebc0_cs2_bxap_value);
 349         mtebc(pb2cr, ebc0_cs2_bxcr_value);
 350
 351         /*--------------------------------------------------------------------+
 352          | Interrupt controller setup for the AMCC 440SPe Evaluation board.
 353          +--------------------------------------------------------------------+
 354         +---------------------------------------------------------------------+
 355         |Interrupt| Source                            | Pol.  | Sensi.| Crit. |
 356         +---------+-----------------------------------+-------+-------+-------+
 357         | IRQ 00  | UART0                             | High  | Level | Non   |
 358         | IRQ 01  | UART1                             | High  | Level | Non   |
 359         | IRQ 02  | IIC0                              | High  | Level | Non   |
 360         | IRQ 03  | IIC1                              | High  | Level | Non   |
 361         | IRQ 04  | PCI0X0 MSG IN                     | High  | Level | Non   |
 362         | IRQ 05  | PCI0X0 CMD Write                  | High  | Level | Non   |
 363         | IRQ 06  | PCI0X0 Power Mgt                  | High  | Level | Non   |
 364         | IRQ 07  | PCI0X0 VPD Access                 | Rising| Edge  | Non   |
 365         | IRQ 08  | PCI0X0 MSI level 0                | High  | Lvl/ed| Non   |
 366         | IRQ 09  | External IRQ 15 - (PCI-Express)   | pgm H | Pgm   | Non   |
 367         | IRQ 10  | UIC2 Non-critical Int.            | NA    | NA    | Non   |
 368         | IRQ 11  | UIC2 Critical Interrupt           | NA    | NA    | Crit  |
 369         | IRQ 12  | PCI Express MSI Level 0           | Rising| Edge  | Non   |
 370         | IRQ 13  | PCI Express MSI Level 1           | Rising| Edge  | Non   |
 371         | IRQ 14  | PCI Express MSI Level 2           | Rising| Edge  | Non   |
 372         | IRQ 15  | PCI Express MSI Level 3           | Rising| Edge  | Non   |
 373         | IRQ 16  | UIC3 Non-critical Int.            | NA    | NA    | Non   |
 374         | IRQ 17  | UIC3 Critical Interrupt           | NA    | NA    | Crit  |
 375         | IRQ 18  | External IRQ 14 - (PCI-Express)   | Pgm   | Pgm   | Non   |
 376         | IRQ 19  | DMA Channel 0 FIFO Full           | High  | Level | Non   |
 377         | IRQ 20  | DMA Channel 0 Stat FIFO           | High  | Level | Non   |
 378         | IRQ 21  | DMA Channel 1 FIFO Full           | High  | Level | Non   |
 379         | IRQ 22  | DMA Channel 1 Stat FIFO           | High  | Level | Non   |
 380         | IRQ 23  | I2O Inbound Doorbell              | High  | Level | Non   |
 381         | IRQ 24  | Inbound Post List FIFO Not Empt   | High  | Level | Non   |
 382         | IRQ 25  | I2O Region 0 LL PLB Write         | High  | Level | Non   |
 383         | IRQ 26  | I2O Region 1 LL PLB Write         | High  | Level | Non   |
 384         | IRQ 27  | I2O Region 0 HB PLB Write         | High  | Level | Non   |
 385         | IRQ 28  | I2O Region 1 HB PLB Write         | High  | Level | Non   |
 386         | IRQ 29  | GPT Down Count Timer              | Rising| Edge  | Non   |
 387         | IRQ 30  | UIC1 Non-critical Int.            | NA    | NA    | Non   |
 388         | IRQ 31  | UIC1 Critical Interrupt           | NA    | NA    | Crit. |
 389         |----------------------------------------------------------------------
 390         | IRQ 32  | Ext. IRQ 13 - (PCI-Express)       |pgm (H)|pgm/Lvl| Non   |
 391         | IRQ 33  | MAL Serr                          | High  | Level | Non   |
 392         | IRQ 34  | MAL Txde                          | High  | Level | Non   |
 393         | IRQ 35  | MAL Rxde                          | High  | Level | Non   |
 394         | IRQ 36  | DMC CE or DMC UE                  | High  | Level | Non   |
 395         | IRQ 37  | EBC or UART2                      | High  |Lvl Edg| Non   |
 396         | IRQ 38  | MAL TX EOB                        | High  | Level | Non   |
 397         | IRQ 39  | MAL RX EOB                        | High  | Level | Non   |
 398         | IRQ 40  | PCIX0 MSI Level 1                 | High  |Lvl Edg| Non   |
 399         | IRQ 41  | PCIX0 MSI level 2                 | High  |Lvl Edg| Non   |
 400         | IRQ 42  | PCIX0 MSI level 3                 | High  |Lvl Edg| Non   |
 401         | IRQ 43  | L2 Cache                          | Risin | Edge  | Non   |
 402         | IRQ 44  | GPT Compare Timer 0               | Risin | Edge  | Non   |
 403         | IRQ 45  | GPT Compare Timer 1               | Risin | Edge  | Non   |
 404         | IRQ 46  | GPT Compare Timer 2               | Risin | Edge  | Non   |
 405         | IRQ 47  | GPT Compare Timer 3               | Risin | Edge  | Non   |
 406         | IRQ 48  | GPT Compare Timer 4               | Risin | Edge  | Non   |
 407         | IRQ 49  | Ext. IRQ 12 - PCI-X               |pgm/Fal|pgm/Lvl| Non   |
 408         | IRQ 50  | Ext. IRQ 11 -                     |pgm (H)|pgm/Lvl| Non   |
 409         | IRQ 51  | Ext. IRQ 10 -                     |pgm (H)|pgm/Lvl| Non   |
 410         | IRQ 52  | Ext. IRQ 9                        |pgm (H)|pgm/Lvl| Non   |
 411         | IRQ 53  | Ext. IRQ 8                        |pgm (H)|pgm/Lvl| Non   |
 412         | IRQ 54  | DMA Error                         | High  | Level | Non   |
 413         | IRQ 55  | DMA I2O Error                     | High  | Level | Non   |
 414         | IRQ 56  | Serial ROM                        | High  | Level | Non   |
 415         | IRQ 57  | PCIX0 Error                       | High  | Edge  | Non   |
 416         | IRQ 58  | Ext. IRQ 7-                       |pgm (H)|pgm/Lvl| Non   |
 417         | IRQ 59  | Ext. IRQ 6-                       |pgm (H)|pgm/Lvl| Non   |
 418         | IRQ 60  | EMAC0 Interrupt                   | High  | Level | Non   |
 419         | IRQ 61  | EMAC0 Wake-up                     | High  | Level | Non   |
 420         | IRQ 62  | Reserved                          | High  | Level | Non   |
 421         | IRQ 63  | XOR                               | High  | Level | Non   |
 422         |----------------------------------------------------------------------
 423         | IRQ 64  | PE0 AL                            | High  | Level | Non   |
 424         | IRQ 65  | PE0 VPD Access                    | Risin | Edge  | Non   |
 425         | IRQ 66  | PE0 Hot Reset Request             | Risin | Edge  | Non   |
 426         | IRQ 67  | PE0 Hot Reset Request             | Falli | Edge  | Non   |
 427         | IRQ 68  | PE0 TCR                           | High  | Level | Non   |
 428         | IRQ 69  | PE0 BusMaster VCO                 | Falli | Edge  | Non   |
 429         | IRQ 70  | PE0 DCR Error                     | High  | Level | Non   |
 430         | IRQ 71  | Reserved                          | N/A   | N/A   | Non   |
 431         | IRQ 72  | PE1 AL                            | High  | Level | Non   |
 432         | IRQ 73  | PE1 VPD Access                    | Risin | Edge  | Non   |
 433         | IRQ 74  | PE1 Hot Reset Request             | Risin | Edge  | Non   |
 434         | IRQ 75  | PE1 Hot Reset Request             | Falli | Edge  | Non   |
 435         | IRQ 76  | PE1 TCR                           | High  | Level | Non   |
 436         | IRQ 77  | PE1 BusMaster VCO                 | Falli | Edge  | Non   |
 437         | IRQ 78  | PE1 DCR Error                     | High  | Level | Non   |
 438         | IRQ 79  | Reserved                          | N/A   | N/A   | Non   |
 439         | IRQ 80  | PE2 AL                            | High  | Level | Non   |
 440         | IRQ 81  | PE2 VPD Access                    | Risin | Edge  | Non   |
 441         | IRQ 82  | PE2 Hot Reset Request             | Risin | Edge  | Non   |
 442         | IRQ 83  | PE2 Hot Reset Request             | Falli | Edge  | Non   |
 443         | IRQ 84  | PE2 TCR                           | High  | Level | Non   |
 444         | IRQ 85  | PE2 BusMaster VCO                 | Falli | Edge  | Non   |
 445         | IRQ 86  | PE2 DCR Error                     | High  | Level | Non   |
 446         | IRQ 87  | Reserved                          | N/A   | N/A   | Non   |
 447         | IRQ 88  | External IRQ(5)                   | Progr | Progr | Non   |
 448         | IRQ 89  | External IRQ 4 - Ethernet         | Progr | Progr | Non   |
 449         | IRQ 90  | External IRQ 3 - PCI-X            | Progr | Progr | Non   |
 450         | IRQ 91  | External IRQ 2 - PCI-X            | Progr | Progr | Non   |
 451         | IRQ 92  | External IRQ 1 - PCI-X            | Progr | Progr | Non   |
 452         | IRQ 93  | External IRQ 0 - PCI-X            | Progr | Progr | Non   |
 453         | IRQ 94  | Reserved                          | N/A   | N/A   | Non   |
 454         | IRQ 95  | Reserved                          | N/A   | N/A   | Non   |
 455         |---------------------------------------------------------------------
 456         | IRQ 96  | PE0 INTA                          | High  | Level | Non   |
 457         | IRQ 97  | PE0 INTB                          | High  | Level | Non   |
 458         | IRQ 98  | PE0 INTC                          | High  | Level | Non   |
 459         | IRQ 99  | PE0 INTD                          | High  | Level | Non   |
 460         | IRQ 100 | PE1 INTA                          | High  | Level | Non   |
 461         | IRQ 101 | PE1 INTB                          | High  | Level | Non   |
 462         | IRQ 102 | PE1 INTC                          | High  | Level | Non   |
 463         | IRQ 103 | PE1 INTD                          | High  | Level | Non   |
 464         | IRQ 104 | PE2 INTA                          | High  | Level | Non   |
 465         | IRQ 105 | PE2 INTB                          | High  | Level | Non   |
 466         | IRQ 106 | PE2 INTC                          | High  | Level | Non   |
 467         | IRQ 107 | PE2 INTD                          | Risin | Edge  | Non   |
 468         | IRQ 108 | PCI Express MSI Level 4           | Risin | Edge  | Non   |
 469         | IRQ 109 | PCI Express MSI Level 5           | Risin | Edge  | Non   |
 470         | IRQ 110 | PCI Express MSI Level 6           | Risin | Edge  | Non   |
 471         | IRQ 111 | PCI Express MSI Level 7           | Risin | Edge  | Non   |
 472         | IRQ 116 | PCI Express MSI Level 12          | Risin | Edge  | Non   |
 473         | IRQ 112 | PCI Express MSI Level 8           | Risin | Edge  | Non   |
 474         | IRQ 113 | PCI Express MSI Level 9           | Risin | Edge  | Non   |
 475         | IRQ 114 | PCI Express MSI Level 10          | Risin | Edge  | Non   |
 476         | IRQ 115 | PCI Express MSI Level 11          | Risin | Edge  | Non   |
 477         | IRQ 117 | PCI Express MSI Level 13          | Risin | Edge  | Non   |
 478         | IRQ 118 | PCI Express MSI Level 14          | Risin | Edge  | Non   |
 479         | IRQ 119 | PCI Express MSI Level 15          | Risin | Edge  | Non   |
 480         | IRQ 120 | PCI Express MSI Level 16          | Risin | Edge  | Non   |
 481         | IRQ 121 | PCI Express MSI Level 17          | Risin | Edge  | Non   |
 482         | IRQ 122 | PCI Express MSI Level 18          | Risin | Edge  | Non   |
 483         | IRQ 123 | PCI Express MSI Level 19          | Risin | Edge  | Non   |
 484         | IRQ 124 | PCI Express MSI Level 20          | Risin | Edge  | Non   |
 485         | IRQ 125 | PCI Express MSI Level 21          | Risin | Edge  | Non   |
 486         | IRQ 126 | PCI Express MSI Level 22          | Risin | Edge  | Non   |
 487         | IRQ 127 | PCI Express MSI Level 23          | Risin | Edge  | Non   |
 488         +---------+-----------------------------------+-------+-------+------*/
 489         /*--------------------------------------------------------------------+
 490          | Put UICs in PowerPC440SPemode.
 491          | Initialise UIC registers.  Clear all interrupts.  Disable all
 492          | interrupts.
 493          | Set critical interrupt values.  Set interrupt polarities.  Set
 494          | interrupt trigger levels.  Make bit 0 High  priority.  Clear all
 495          | interrupts again.
 496          +-------------------------------------------------------------------*/
 497         mtdcr (uic3sr, 0xffffffff);     /* Clear all interrupts */
 498         mtdcr (uic3er, 0x00000000);     /* disable all interrupts */
 499         mtdcr (uic3cr, 0x00000000);     /* Set Critical / Non Critical
 500                                          * interrupts */
 501         mtdcr (uic3pr, 0xffffffff);     /* Set Interrupt Polarities */
 502         mtdcr (uic3tr, 0x001fffff);     /* Set Interrupt Trigger Levels */
 503         mtdcr (uic3vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
 504                                          * priority */
 505         mtdcr (uic3sr, 0x00000000);     /* clear all  interrupts */
 506         mtdcr (uic3sr, 0xffffffff);     /* clear all  interrupts */
 507
 508         mtdcr (uic2sr, 0xffffffff);     /* Clear all interrupts */
 509         mtdcr (uic2er, 0x00000000);     /* disable all interrupts */
 510         mtdcr (uic2cr, 0x00000000);     /* Set Critical / Non Critical
 511                                          * interrupts */
 512         mtdcr (uic2pr, 0xebebebff);     /* Set Interrupt Polarities */
 513         mtdcr (uic2tr, 0x74747400);     /* Set Interrupt Trigger Levels */
 514         mtdcr (uic2vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
 515                                          * priority */
 516         mtdcr (uic2sr, 0x00000000);     /* clear all interrupts */
 517         mtdcr (uic2sr, 0xffffffff);     /* clear all interrupts */
 518
 519         mtdcr (uic1sr, 0xffffffff);     /* Clear all interrupts */
 520         mtdcr (uic1er, 0x00000000);     /* disable all interrupts */
 521         mtdcr (uic1cr, 0x00000000);     /* Set Critical / Non Critical
 522                                          * interrupts */
 523         mtdcr (uic1pr, 0xffffffff);     /* Set Interrupt Polarities */
 524         mtdcr (uic1tr, 0x001f8040);     /* Set Interrupt Trigger Levels */
 525         mtdcr (uic1vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
 526                                          * priority */
 527         mtdcr (uic1sr, 0x00000000);     /* clear all interrupts */
 528         mtdcr (uic1sr, 0xffffffff);     /* clear all interrupts */
 529
 530         mtdcr (uic0sr, 0xffffffff);     /* Clear all interrupts */
 531         mtdcr (uic0er, 0x00000000);     /* disable all interrupts excepted
 532                                          * cascade to be checked */
 533         mtdcr (uic0cr, 0x00104001);     /* Set Critical / Non Critical
 534                                          * interrupts */
 535         mtdcr (uic0pr, 0xffffffff);     /* Set Interrupt Polarities */
 536         mtdcr (uic0tr, 0x010f0004);     /* Set Interrupt Trigger Levels */
 537         mtdcr (uic0vr, 0x00000001);     /* Set Vect base=0,INT31 Highest
 538                                          * priority */
 539         mtdcr (uic0sr, 0x00000000);     /* clear all interrupts */
 540         mtdcr (uic0sr, 0xffffffff);     /* clear all interrupts */
 541
 542         /* SDR0_MFR should be part of Ethernet init */
 543         mfsdr (sdr_mfr, mfr);
 544         mfr &= ~SDR0_MFR_ECS_MASK;
 545         /*mtsdr(sdr_mfr, mfr);*/
 546         fpga_init();
 547
 548         return 0;
 549 }
 550
 551 int checkboard (void)
 552 {
 553         char *s = getenv("serial#");
 554
 555         printf("Board: Yucca - AMCC 440SPe Evaluation Board");
 556         if (s != NULL) {
 557                 puts(", serial# ");
 558                 puts(s);
 559         }
 560         putc('\n');
 561
 562         return 0;
 563 }
 564
 565 #if defined(CFG_DRAM_TEST)
 566 int testdram (void)
 567 {
 568         uint *pstart = (uint *) 0x00000000;
 569         uint *pend = (uint *) 0x08000000;
 570         uint *p;
 571
 572         for (p = pstart; p < pend; p++)
 573                 *p = 0xaaaaaaaa;
 574
 575         for (p = pstart; p < pend; p++) {
 576                 if (*p != 0xaaaaaaaa) {
 577                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 578                         return 1;
 579                 }
 580         }
 581
 582         for (p = pstart; p < pend; p++)
 583                 *p = 0x55555555;
 584
 585         for (p = pstart; p < pend; p++) {
 586                 if (*p != 0x55555555) {
 587                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 588                         return 1;
 589                 }
 590         }
 591         return 0;
 592 }
 593 #endif
 594
 595 /*************************************************************************
 596  *  pci_pre_init
 597  *
 598  *  This routine is called just prior to registering the hose and gives
 599  *  the board the opportunity to check things. Returning a value of zero
 600  *  indicates that things are bad & PCI initialization should be aborted.
 601  *
 602  *      Different boards may wish to customize the pci controller structure
 603  *      (add regions, override default access routines, etc) or perform
 604  *      certain pre-initialization actions.
 605  *
 606  ************************************************************************/
 607 #if defined(CONFIG_PCI)
 608 int pci_pre_init(struct pci_controller * hose )
 609 {
 610         unsigned long strap;
 611
 612         /*-------------------------------------------------------------------+
 613          *      The yucca board is always configured as the host & requires the
 614          *      PCI arbiter to be enabled.
 615          *-------------------------------------------------------------------*/
 616         mfsdr(sdr_sdstp1, strap);
 617         if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
 618                 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
 619                 return 0;
 620         }
 621
 622         return 1;
 623 }
 624 #endif  /* defined(CONFIG_PCI) */
 625
 626 /*************************************************************************
 627  *  pci_target_init
 628  *
 629  *      The bootstrap configuration provides default settings for the pci
 630  *      inbound map (PIM). But the bootstrap config choices are limited and
 631  *      may not be sufficient for a given board.
 632  *
 633  ************************************************************************/
 634 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 635 void pci_target_init(struct pci_controller * hose )
 636 {
 637         DECLARE_GLOBAL_DATA_PTR;
 638
 639         /*-------------------------------------------------------------------+
 640          * Disable everything
 641          *-------------------------------------------------------------------*/
 642         out32r( PCIX0_PIM0SA, 0 ); /* disable */
 643         out32r( PCIX0_PIM1SA, 0 ); /* disable */
 644         out32r( PCIX0_PIM2SA, 0 ); /* disable */
 645         out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
 646
 647         /*-------------------------------------------------------------------+
 648          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 649          * strapping options to not support sizes such as 128/256 MB.
 650          *-------------------------------------------------------------------*/
 651         out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
 652         out32r( PCIX0_PIM0LAH, 0 );
 653         out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 654         out32r( PCIX0_BAR0, 0 );
 655
 656         /*-------------------------------------------------------------------+
 657          * Program the board's subsystem id/vendor id
 658          *-------------------------------------------------------------------*/
 659         out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
 660         out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
 661
 662         out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 663 }
 664 #endif  /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 665
 666 #if defined(CONFIG_PCI)
 667 /*************************************************************************
 668  *  is_pci_host
 669  *
 670  *      This routine is called to determine if a pci scan should be
 671  *      performed. With various hardware environments (especially cPCI and
 672  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 673  *      bit in the strap register, or generic host/adapter assumptions.
 674  *
 675  *      Rather than hard-code a bad assumption in the general 440 code, the
 676  *      440 pci code requires the board to decide at runtime.
 677  *
 678  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 679  *
 680  *
 681  ************************************************************************/
 682 int is_pci_host(struct pci_controller *hose)
 683 {
 684         /* The yucca board is always configured as host. */
 685         return 1;
 686 }
 687
 688 int yucca_pcie_card_present(int port)
 689 {
 690         u16 reg;
 691
 692         reg = in_be16((u16 *)FPGA_REG1C);
 693         switch(port) {
 694         case 0:
 695                 return !(reg & FPGA_REG1C_PE0_PRSNT);
 696         case 1:
 697                 return !(reg & FPGA_REG1C_PE1_PRSNT);
 698         case 2:
 699                 return !(reg & FPGA_REG1C_PE2_PRSNT);
 700         default:
 701                 return 0;
 702         }
 703 }
 704
 705 /*
 706  * For the given slot, set rootpoint mode, send power to the slot,
 707  * turn on the green LED and turn off the yellow LED, enable the clock
 708  * and turn off reset.
 709  */
 710 void yucca_setup_pcie_fpga_rootpoint(int port)
 711 {
 712         u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
 713
 714         switch(port) {
 715         case 0:
 716                 rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
 717                 endpoint    = 0;
 718                 power       = FPGA_REG1A_PE0_PWRON;
 719                 green_led   = FPGA_REG1A_PE0_GLED;
 720                 clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
 721                 yellow_led  = FPGA_REG1A_PE0_YLED;
 722                 reset_off   = FPGA_REG1C_PE0_PERST;
 723                 break;
 724         case 1:
 725                 rootpoint   = 0;
 726                 endpoint    = FPGA_REG1C_PE1_ENDPOINT;
 727                 power       = FPGA_REG1A_PE1_PWRON;
 728                 green_led   = FPGA_REG1A_PE1_GLED;
 729                 clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
 730                 yellow_led  = FPGA_REG1A_PE1_YLED;
 731                 reset_off   = FPGA_REG1C_PE1_PERST;
 732                 break;
 733         case 2:
 734                 rootpoint   = 0;
 735                 endpoint    = FPGA_REG1C_PE2_ENDPOINT;
 736                 power       = FPGA_REG1A_PE2_PWRON;
 737                 green_led   = FPGA_REG1A_PE2_GLED;
 738                 clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
 739                 yellow_led  = FPGA_REG1A_PE2_YLED;
 740                 reset_off   = FPGA_REG1C_PE2_PERST;
 741                 break;
 742
 743         default:
 744                 return;
 745         }
 746
 747         out_be16((u16 *)FPGA_REG1A,
 748                  ~(power | clock | green_led) &
 749                  (yellow_led | in_be16((u16 *)FPGA_REG1A)));
 750
 751         out_be16((u16 *)FPGA_REG1C,
 752                  ~(endpoint | reset_off) &
 753                  (rootpoint | in_be16((u16 *)FPGA_REG1C)));
 754         /*
 755          * Leave device in reset for a while after powering on the
 756          * slot to give it a chance to initialize.
 757          */
 758         udelay(250 * 1000);
 759
 760         out_be16((u16 *)FPGA_REG1C, reset_off | in_be16((u16 *)FPGA_REG1C));
 761 }
 762 /*
 763  * For the given slot, set endpoint mode, send power to the slot,
 764  * turn on the green LED and turn off the yellow LED, enable the clock
 765  * .In end point mode reset bit is  read only.
 766  */
 767 void yucca_setup_pcie_fpga_endpoint(int port)
 768 {
 769         u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
 770
 771         switch(port) {
 772         case 0:
 773                 rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
 774                 endpoint    = 0;
 775                 power       = FPGA_REG1A_PE0_PWRON;
 776                 green_led   = FPGA_REG1A_PE0_GLED;
 777                 clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
 778                 yellow_led  = FPGA_REG1A_PE0_YLED;
 779                 reset_off   = FPGA_REG1C_PE0_PERST;
 780                 break;
 781         case 1:
 782                 rootpoint   = 0;
 783                 endpoint    = FPGA_REG1C_PE1_ENDPOINT;
 784                 power       = FPGA_REG1A_PE1_PWRON;
 785                 green_led   = FPGA_REG1A_PE1_GLED;
 786                 clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
 787                 yellow_led  = FPGA_REG1A_PE1_YLED;
 788                 reset_off   = FPGA_REG1C_PE1_PERST;
 789                 break;
 790         case 2:
 791                 rootpoint   = 0;
 792                 endpoint    = FPGA_REG1C_PE2_ENDPOINT;
 793                 power       = FPGA_REG1A_PE2_PWRON;
 794                 green_led   = FPGA_REG1A_PE2_GLED;
 795                 clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
 796                 yellow_led  = FPGA_REG1A_PE2_YLED;
 797                 reset_off   = FPGA_REG1C_PE2_PERST;
 798                 break;
 799
 800         default:
 801                 return;
 802         }
 803
 804         out_be16((u16 *)FPGA_REG1A,
 805                  ~(power | clock | green_led) &
 806                  (yellow_led | in_be16((u16 *)FPGA_REG1A)));
 807
 808         out_be16((u16 *)FPGA_REG1C,
 809                  ~(rootpoint | reset_off) &
 810                  (endpoint | in_be16((u16 *)FPGA_REG1C)));
 811 }
 812
 813 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
 814
 815 void pcie_setup_hoses(void)
 816 {
 817         struct pci_controller *hose;
 818         int i, bus;
 819
 820         /*
 821          * assume we're called after the PCIX hose is initialized, which takes
 822          * bus ID 0 and therefore start numbering PCIe's from 1.
 823          */
 824         bus = 1;
 825         for (i = 0; i <= 2; i++) {
 826                 /* Check for yucca card presence */
 827                 if (!yucca_pcie_card_present(i))
 828                         continue;
 829
 830 #ifdef PCIE_ENDPOINT
 831                 yucca_setup_pcie_fpga_endpoint(i);
 832                 if (ppc440spe_init_pcie_endport(i)) {
 833 #else
 834                 yucca_setup_pcie_fpga_rootpoint(i);
 835                 if (ppc440spe_init_pcie_rootport(i)) {
 836 #endif
 837                         printf("PCIE%d: initialization failed\n", i);
 838                         continue;
 839                 }
 840
 841                 hose = &pcie_hose[i];
 842                 hose->first_busno = bus;
 843                 hose->last_busno  = bus;
 844                 bus++;
 845
 846                 /* setup mem resource */
 847                 pci_set_region(hose->regions + 0,
 848                         CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
 849                         CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
 850                         CFG_PCIE_MEMSIZE,
 851                         PCI_REGION_MEM
 852                         );
 853                 hose->region_count = 1;
 854                 pci_register_hose(hose);
 855
 856 #ifdef PCIE_ENDPOINT
 857                 ppc440spe_setup_pcie_endpoint(hose, i);
 858                 /*
 859                  * Reson for no scanning is endpoint can not generate
 860                  * upstream configuration accesses.
 861                  */
 862 #else
 863                 ppc440spe_setup_pcie_rootpoint(hose, i);
 864                 /*
 865                  * Config access can only go down stream
 866                  */
 867                 hose->last_busno = pci_hose_scan(hose);
 868 #endif
 869         }
 870 }
 871 #endif  /* defined(CONFIG_PCI) */
 872
 873 int misc_init_f (void)
 874 {
 875         uint reg;
 876 #if defined(CONFIG_STRESS)
 877         uint i ;
 878         uint disp;
 879 #endif
 880
 881         out16(FPGA_REG10, (in16(FPGA_REG10) &
 882                         ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
 883                                 FPGA_REG10_10MHZ_ENABLE |
 884                                 FPGA_REG10_100MHZ_ENABLE |
 885                                 FPGA_REG10_GIGABIT_ENABLE |
 886                                 FPGA_REG10_FULL_DUPLEX );
 887
 888         udelay(10000);  /* wait 10ms */
 889
 890         out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH));
 891
 892         /* minimal init for PCIe */
 893         /* pci express 0 Endpoint Mode */
 894         mfsdr(SDR0_PE0DLPSET, reg);
 895         reg &= (~0x00400000);
 896         mtsdr(SDR0_PE0DLPSET, reg);
 897         /* pci express 1 Rootpoint  Mode */
 898         mfsdr(SDR0_PE1DLPSET, reg);
 899         reg |= 0x00400000;
 900         mtsdr(SDR0_PE1DLPSET, reg);
 901         /* pci express 2 Rootpoint  Mode */
 902         mfsdr(SDR0_PE2DLPSET, reg);
 903         reg |= 0x00400000;
 904         mtsdr(SDR0_PE2DLPSET, reg);
 905
 906         out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
 907                                 ~FPGA_REG1C_PE0_ROOTPOINT &
 908                                 ~FPGA_REG1C_PE1_ENDPOINT  &
 909                                 ~FPGA_REG1C_PE2_ENDPOINT));
 910
 911 #if defined(CONFIG_STRESS)
 912         /*
 913          * all this setting done by linux only needed by stress an charac. test
 914          * procedure
 915          * PCIe 1 Rootpoint PCIe2 Endpoint
 916          * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
 917          * Power Level
 918          */
 919         for (i = 0, disp = 0; i < 8; i++, disp += 3) {
 920                 mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
 921                 reg |= 0x33000000;
 922                 mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
 923         }
 924
 925         /*
 926          * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
 927          * Power Level
 928          */
 929         for (i = 0, disp = 0; i < 4; i++, disp += 3) {
 930                 mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
 931                 reg |= 0x33000000;
 932                 mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
 933         }
 934
 935         /*
 936          * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
 937          * Power Level
 938          */
 939         for (i = 0, disp = 0; i < 4; i++, disp += 3) {
 940                 mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
 941                 reg |= 0x33000000;
 942                 mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
 943         }
 944
 945         reg = 0x21242222;
 946         mtsdr(SDR0_PE2UTLSET1, reg);
 947         reg = 0x11000000;
 948         mtsdr(SDR0_PE2UTLSET2, reg);
 949         /* pci express 1 Endpoint  Mode */
 950         reg = 0x00004000;
 951         mtsdr(SDR0_PE2DLPSET, reg);
 952
 953         mtsdr(SDR0_UART1, 0x2080005a);  /* patch for TG */
 954 #endif
 955         return 0;
 956 }
 957
 958 void fpga_init(void)
 959 {
 960         /*
 961          * by default sdram access is disabled by fpga
 962          */
 963         out16(FPGA_REG10, (in16 (FPGA_REG10) |
 964                                 FPGA_REG10_SDRAM_ENABLE |
 965                                 FPGA_REG10_ENABLE_DISPLAY ));
 966
 967         return;
 968 }
 969
 970 #ifdef CONFIG_POST
 971 /*
 972  * Returns 1 if keys pressed to start the power-on long-running tests
 973  * Called from board_init_f().
 974  */
 975 int post_hotkeys_pressed(void)
 976 {
 977         return (ctrlc());
 978 }
 979 #endif
 980
 981 /*---------------------------------------------------------------------------+
 982  | onboard_pci_arbiter_selected => from EPLD
 983  +---------------------------------------------------------------------------*/
 984 int onboard_pci_arbiter_selected(int core_pci)
 985 {
 986 #if 0
 987         unsigned long onboard_pci_arbiter_sel;
 988
 989         onboard_pci_arbiter_sel = in16(FPGA_REG0) & FPGA_REG0_EXT_ARB_SEL_MASK;
 990
 991         if (onboard_pci_arbiter_sel == FPGA_REG0_EXT_ARB_SEL_EXTERNAL)
 992                 return (BOARD_OPTION_SELECTED);
 993         else
 994 #endif
 995         return (BOARD_OPTION_NOT_SELECTED);
 996 }