3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
25 #include <spd_sdram.h>
27 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
29 int board_early_init_f(void)
33 /*--------------------------------------------------------------------
34 * Setup the external bus controller/chip selects
35 *-------------------------------------------------------------------*/
36 mtdcr(ebccfga, xbcfg);
38 mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
40 mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
41 mtebc(pb0cr, 0xfc0da000); /* BAS=0xfc0 64MB r/w 16-bit */
43 mtebc(pb1ap, 0x00000000);
44 mtebc(pb1cr, 0x00000000);
46 mtebc(pb2ap, 0x04814500);
47 /*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
49 mtebc(pb3ap, 0x00000000);
50 mtebc(pb3cr, 0x00000000);
52 mtebc(pb4ap, 0x00000000);
53 mtebc(pb4cr, 0x00000000);
55 mtebc(pb5ap, 0x00000000);
56 mtebc(pb5cr, 0x00000000);
58 /*--------------------------------------------------------------------
60 *-------------------------------------------------------------------*/
62 /*setup Address lines for flash size 64Meg. */
63 out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
64 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
65 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
68 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
69 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
70 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
71 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
72 out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
75 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
76 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
77 out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
79 /* external interrupts IRQ0...3 */
80 out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x0f000000);
81 out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x00005500);
82 out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
85 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
86 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
87 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
88 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
89 out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
91 /*--------------------------------------------------------------------
92 * Setup the interrupt controller polarities, triggers, etc.
93 *-------------------------------------------------------------------*/
94 mtdcr(uic0sr, 0xffffffff); /* clear all */
95 mtdcr(uic0er, 0x00000000); /* disable all */
96 mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
97 mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
98 mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
99 mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
100 mtdcr(uic0sr, 0xffffffff); /* clear all */
102 mtdcr(uic1sr, 0xffffffff); /* clear all */
103 mtdcr(uic1er, 0x00000000); /* disable all */
104 mtdcr(uic1cr, 0x00000000); /* all non-critical */
105 mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
106 mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
107 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
108 mtdcr(uic1sr, 0xffffffff); /* clear all */
110 /*--------------------------------------------------------------------
111 * Setup other serial configuration
112 *-------------------------------------------------------------------*/
113 mfsdr(sdr_pci0, reg);
114 mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
115 mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
116 mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
118 /*clear tmrclk divisor */
119 *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
122 *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
124 /*enable usb 1.1 fs device and remove usb 2.0 reset */
125 *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
127 /*get rid of flash write protect */
128 *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
133 int misc_init_r (void)
135 DECLARE_GLOBAL_DATA_PTR;
139 /* Re-do sizing to get full correct info */
140 mtdcr(ebccfga, pb0cr);
141 pbcr = mfdcr(ebccfgd);
142 switch (gd->bd->bi_flashsize) {
168 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
169 mtdcr(ebccfga, pb0cr);
170 mtdcr(ebccfgd, pbcr);
172 /* adjust flash start and offset */
173 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
174 gd->bd->bi_flashoffset = 0;
176 /* Monitor protection ON by default */
177 (void)flash_protect(FLAG_PROTECT_SET,
187 char *s = getenv("serial#");
189 printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
199 /*************************************************************************
200 * sdram_init -- doesn't use serial presence detect.
202 * Assumes: 256 MB, ECC, non-registered
205 ************************************************************************/
209 void sdram_tr1_set(int ram_address, int* tr1_value)
213 volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
214 int first_good = -1, last_bad = 0x1ff;
216 unsigned long test[NUM_TRIES] = {
217 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
218 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
219 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
220 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
221 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
222 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
223 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
224 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
225 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
226 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
227 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
228 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
229 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
230 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
231 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
232 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
234 /* go through all possible SDRAM0_TR1[RDCT] values */
235 for (i=0; i<=0x1ff; i++) {
236 /* set the current value for TR1 */
237 mtsdram(mem_tr1, (0x80800800 | i));
240 for (j=0; j<NUM_TRIES; j++) {
241 ram_pointer[j] = test[j];
243 /* clear any cache at ram location */
244 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
247 /* read values back */
248 for (j=0; j<NUM_TRIES; j++) {
249 for (k=0; k<NUM_READS; k++) {
250 /* clear any cache at ram location */
251 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
253 if (ram_pointer[j] != test[j])
258 if (k != NUM_READS) {
263 /* we have a SDRAM0_TR1[RDCT] that is part of the window */
264 if (j == NUM_TRIES) {
265 if (first_good == -1)
266 first_good = i; /* found beginning of window */
267 } else { /* bad read */
268 /* if we have not had a good read then don't care */
269 if(first_good != -1) {
270 /* first failure after a good read */
277 /* return the current value for TR1 */
278 *tr1_value = (first_good + last_bad) / 2;
281 void sdram_init(void)
284 int tr1_bank1, tr1_bank2;
286 /*--------------------------------------------------------------------
288 *------------------------------------------------------------------*/
289 mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
290 mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
291 mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
292 mtsdram(mem_clktr, 0x40000000); /* ?? */
293 mtsdram(mem_wddctr, 0x40000000); /* ?? */
295 /*clear this first, if the DDR is enabled by a debugger
296 then you can not make changes. */
297 mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
299 /*--------------------------------------------------------------------
300 * Setup for board-specific specific mem
301 *------------------------------------------------------------------*/
303 * Following for CAS Latency = 2.5 @ 133 MHz PLB
305 mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
306 mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
308 mtsdram(mem_tr0, 0x410a4012); /* ?? */
309 mtsdram(mem_rtr, 0x04080000); /* ?? */
310 mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
311 mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
312 udelay(400); /* Delay 200 usecs (min) */
314 /*--------------------------------------------------------------------
315 * Enable the controller, then wait for DCEN to complete
316 *------------------------------------------------------------------*/
317 mtsdram(mem_cfg0, 0x84000000); /* Enable */
320 mfsdram(mem_mcsts, reg);
321 if (reg & 0x80000000)
325 sdram_tr1_set(0x00000000, &tr1_bank1);
326 sdram_tr1_set(0x08000000, &tr1_bank2);
327 mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );
330 /*************************************************************************
333 ************************************************************************/
334 long int initdram(int board)
337 return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
340 #if defined(CFG_DRAM_TEST)
343 unsigned long *mem = (unsigned long *)0;
344 const unsigned long kend = (1024 / sizeof(unsigned long));
349 for (k = 0; k < CFG_KBYTES_SDRAM;
350 ++k, mem += (1024 / sizeof(unsigned long))) {
351 if ((k & 1023) == 0) {
352 printf("%3d MB\r", k / 1024);
355 memset(mem, 0xaaaaaaaa, 1024);
356 for (n = 0; n < kend; ++n) {
357 if (mem[n] != 0xaaaaaaaa) {
358 printf("SDRAM test fails at: %08x\n",
364 memset(mem, 0x55555555, 1024);
365 for (n = 0; n < kend; ++n) {
366 if (mem[n] != 0x55555555) {
367 printf("SDRAM test fails at: %08x\n",
373 printf("SDRAM test passes\n");
378 /*************************************************************************
381 * This routine is called just prior to registering the hose and gives
382 * the board the opportunity to check things. Returning a value of zero
383 * indicates that things are bad & PCI initialization should be aborted.
385 * Different boards may wish to customize the pci controller structure
386 * (add regions, override default access routines, etc) or perform
387 * certain pre-initialization actions.
389 ************************************************************************/
390 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
391 int pci_pre_init(struct pci_controller *hose)
395 /*-------------------------------------------------------------------------+
396 | Set priority for all PLB3 devices to 0.
397 | Set PLB3 arbiter to fair mode.
398 +-------------------------------------------------------------------------*/
399 mfsdr(sdr_amp1, addr);
400 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
401 addr = mfdcr(plb3_acr);
402 mtdcr(plb3_acr, addr | 0x80000000);
404 /*-------------------------------------------------------------------------+
405 | Set priority for all PLB4 devices to 0.
406 +-------------------------------------------------------------------------*/
407 mfsdr(sdr_amp0, addr);
408 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
409 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
410 mtdcr(plb4_acr, addr);
412 /*-------------------------------------------------------------------------+
413 | Set Nebula PLB4 arbiter to fair mode.
414 +-------------------------------------------------------------------------*/
416 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
417 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
418 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
419 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
420 mtdcr(plb0_acr, addr);
423 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
424 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
425 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
426 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
427 mtdcr(plb1_acr, addr);
431 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
433 /*************************************************************************
436 * The bootstrap configuration provides default settings for the pci
437 * inbound map (PIM). But the bootstrap config choices are limited and
438 * may not be sufficient for a given board.
440 ************************************************************************/
441 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
442 void pci_target_init(struct pci_controller *hose)
444 /*--------------------------------------------------------------------------+
445 * Set up Direct MMIO registers
446 *--------------------------------------------------------------------------*/
447 /*--------------------------------------------------------------------------+
448 | PowerPC440 EP PCI Master configuration.
449 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
450 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
451 | Use byte reversed out routines to handle endianess.
452 | Make this region non-prefetchable.
453 +--------------------------------------------------------------------------*/
454 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
455 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
456 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
457 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
458 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
460 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
461 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
462 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
463 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
464 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
466 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
467 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
468 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
469 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
471 /*--------------------------------------------------------------------------+
472 * Set up Configuration registers
473 *--------------------------------------------------------------------------*/
475 /* Program the board's subsystem id/vendor id */
476 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
477 CFG_PCI_SUBSYS_VENDORID);
478 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
480 /* Configure command register as bus master */
481 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
483 /* 240nS PCI clock */
484 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
486 /* No error reporting */
487 pci_write_config_word(0, PCI_ERREN, 0);
489 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
492 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
494 /*************************************************************************
497 ************************************************************************/
498 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
499 void pci_master_init(struct pci_controller *hose)
501 unsigned short temp_short;
503 /*--------------------------------------------------------------------------+
504 | Write the PowerPC440 EP PCI Configuration regs.
505 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
506 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
507 +--------------------------------------------------------------------------*/
508 pci_read_config_word(0, PCI_COMMAND, &temp_short);
509 pci_write_config_word(0, PCI_COMMAND,
510 temp_short | PCI_COMMAND_MASTER |
513 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
515 /*************************************************************************
518 * This routine is called to determine if a pci scan should be
519 * performed. With various hardware environments (especially cPCI and
520 * PPMC) it's insufficient to depend on the state of the arbiter enable
521 * bit in the strap register, or generic host/adapter assumptions.
523 * Rather than hard-code a bad assumption in the general 440 code, the
524 * 440 pci code requires the board to decide at runtime.
526 * Return 0 for adapter mode, non-zero for host (monarch) mode.
529 ************************************************************************/
530 #if defined(CONFIG_PCI)
531 int is_pci_host(struct pci_controller *hose)
533 /* Bamboo is always configured as host. */
536 #endif /* defined(CONFIG_PCI) */
538 /*************************************************************************
541 * This routine is called to reset (keep alive) the watchdog timer
543 ************************************************************************/
544 #if defined(CONFIG_HW_WATCHDOG)
545 void hw_watchdog_reset(void)