2 * (C) Copyright 2006-2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <spd_sdram.h>
30 #include <fdt_support.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
36 static inline u32 get_async_pci_freq(void)
38 if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
39 CONFIG_SYS_BCSR5_PCI66EN)
45 int board_early_init_f(void)
49 /*--------------------------------------------------------------------
50 * Setup the external bus controller/chip selects
51 *-------------------------------------------------------------------*/
52 mtdcr(EBC0_CFGADDR, EBC0_CFG);
53 reg = mfdcr(EBC0_CFGDATA);
54 mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
56 /*--------------------------------------------------------------------
58 *-------------------------------------------------------------------*/
60 /*setup Address lines for flash size 64Meg. */
61 out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
62 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
63 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);
66 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
67 out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
68 out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
69 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
70 out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
73 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
74 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
75 out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
77 /* external interrupts IRQ0...3 */
78 out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
79 out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
80 out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);
84 out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
85 out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
86 out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
87 out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
88 out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
91 /*--------------------------------------------------------------------
92 * Setup the interrupt controller polarities, triggers, etc.
93 *-------------------------------------------------------------------*/
94 mtdcr(UIC0SR, 0xffffffff); /* clear all */
95 mtdcr(UIC0ER, 0x00000000); /* disable all */
96 mtdcr(UIC0CR, 0x00000009); /* ATI & UIC1 crit are critical */
97 mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
98 mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
99 mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
100 mtdcr(UIC0SR, 0xffffffff); /* clear all */
102 mtdcr(UIC1SR, 0xffffffff); /* clear all */
103 mtdcr(UIC1ER, 0x00000000); /* disable all */
104 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
105 mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
106 mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
107 mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
108 mtdcr(UIC1SR, 0xffffffff); /* clear all */
110 /*--------------------------------------------------------------------
111 * Setup other serial configuration
112 *-------------------------------------------------------------------*/
113 mfsdr(SDR0_PCI0, reg);
114 mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */
115 mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */
116 mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */
118 /* Check and reconfigure the PCI sync clock if necessary */
119 ppc4xx_pci_sync_clock_config(get_async_pci_freq());
121 /*clear tmrclk divisor */
122 *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;
125 *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0;
128 /*enable usb 1.1 fs device and remove usb 2.0 reset */
129 *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00;
132 /*get rid of flash write protect */
133 *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00;
138 int misc_init_r (void)
143 /* Re-do sizing to get full correct info */
144 mtdcr(EBC0_CFGADDR, PB0CR);
145 pbcr = mfdcr(EBC0_CFGDATA);
146 switch (gd->bd->bi_flashsize) {
172 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
173 mtdcr(EBC0_CFGADDR, PB0CR);
174 mtdcr(EBC0_CFGDATA, pbcr);
176 /* adjust flash start and offset */
177 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
178 gd->bd->bi_flashoffset = 0;
180 /* Monitor protection ON by default */
181 (void)flash_protect(FLAG_PROTECT_SET,
182 -CONFIG_SYS_MONITOR_LEN,
191 char *s = getenv("serial#");
193 u32 clock = get_async_pci_freq();
196 printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");
198 printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
201 rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
202 printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
211 * Reconfiguration of the PCI sync clock is already done,
212 * now check again if everything is in range:
214 if (ppc4xx_pci_sync_clock_config(clock)) {
215 printf("ERROR: PCI clocking incorrect (async=%d "
216 "sync=%ld)!\n", clock, get_PCI_freq());
222 /*************************************************************************
223 * initdram -- doesn't use serial presence detect.
225 * Assumes: 256 MB, ECC, non-registered
228 ************************************************************************/
232 void sdram_tr1_set(int ram_address, int* tr1_value)
236 volatile unsigned int* ram_pointer = (unsigned int*)ram_address;
237 int first_good = -1, last_bad = 0x1ff;
239 unsigned long test[NUM_TRIES] = {
240 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
241 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
242 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
243 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
244 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
245 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
246 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
247 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
248 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
249 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
250 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
251 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
252 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
253 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
254 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
255 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
257 /* go through all possible SDRAM0_TR1[RDCT] values */
258 for (i=0; i<=0x1ff; i++) {
259 /* set the current value for TR1 */
260 mtsdram(SDRAM0_TR1, (0x80800800 | i));
263 for (j=0; j<NUM_TRIES; j++) {
264 ram_pointer[j] = test[j];
266 /* clear any cache at ram location */
267 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
270 /* read values back */
271 for (j=0; j<NUM_TRIES; j++) {
272 for (k=0; k<NUM_READS; k++) {
273 /* clear any cache at ram location */
274 __asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
276 if (ram_pointer[j] != test[j])
281 if (k != NUM_READS) {
286 /* we have a SDRAM0_TR1[RDCT] that is part of the window */
287 if (j == NUM_TRIES) {
288 if (first_good == -1)
289 first_good = i; /* found beginning of window */
290 } else { /* bad read */
291 /* if we have not had a good read then don't care */
292 if(first_good != -1) {
293 /* first failure after a good read */
300 /* return the current value for TR1 */
301 *tr1_value = (first_good + last_bad) / 2;
304 phys_size_t initdram(int board)
307 int tr1_bank1, tr1_bank2;
309 /*--------------------------------------------------------------------
311 *------------------------------------------------------------------*/
312 mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
313 mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
314 mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
315 mtsdram(SDRAM0_CLKTR, 0x40000000); /* ?? */
316 mtsdram(SDRAM0_WDDCTR, 0x40000000); /* ?? */
318 /*clear this first, if the DDR is enabled by a debugger
319 then you can not make changes. */
320 mtsdram(SDRAM0_CFG0, 0x00000000); /* Disable EEC */
322 /*--------------------------------------------------------------------
323 * Setup for board-specific specific mem
324 *------------------------------------------------------------------*/
326 * Following for CAS Latency = 2.5 @ 133 MHz PLB
328 mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
329 mtsdram(SDRAM0_B1CR, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
331 mtsdram(SDRAM0_TR0, 0x410a4012); /* ?? */
332 mtsdram(SDRAM0_RTR, 0x04080000); /* ?? */
333 mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
334 mtsdram(SDRAM0_CFG0, 0x30000000); /* Disable EEC */
335 udelay(400); /* Delay 200 usecs (min) */
337 /*--------------------------------------------------------------------
338 * Enable the controller, then wait for DCEN to complete
339 *------------------------------------------------------------------*/
340 mtsdram(SDRAM0_CFG0, 0x80000000); /* Enable */
343 mfsdram(SDRAM0_MCSTS, reg);
344 if (reg & 0x80000000)
348 sdram_tr1_set(0x00000000, &tr1_bank1);
349 sdram_tr1_set(0x08000000, &tr1_bank2);
350 mtsdram(SDRAM0_TR1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
352 return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024); /* return bytes */
355 /*************************************************************************
358 * This routine is called just prior to registering the hose and gives
359 * the board the opportunity to check things. Returning a value of zero
360 * indicates that things are bad & PCI initialization should be aborted.
362 * Different boards may wish to customize the pci controller structure
363 * (add regions, override default access routines, etc) or perform
364 * certain pre-initialization actions.
366 ************************************************************************/
367 #if defined(CONFIG_PCI)
368 int pci_pre_init(struct pci_controller *hose)
372 /*-------------------------------------------------------------------------+
373 | Set priority for all PLB3 devices to 0.
374 | Set PLB3 arbiter to fair mode.
375 +-------------------------------------------------------------------------*/
376 mfsdr(SD0_AMP1, addr);
377 mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
378 addr = mfdcr(PLB3_ACR);
379 mtdcr(PLB3_ACR, addr | 0x80000000);
381 /*-------------------------------------------------------------------------+
382 | Set priority for all PLB4 devices to 0.
383 +-------------------------------------------------------------------------*/
384 mfsdr(SD0_AMP0, addr);
385 mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
386 addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
387 mtdcr(PLB4_ACR, addr);
389 /*-------------------------------------------------------------------------+
390 | Set Nebula PLB4 arbiter to fair mode.
391 +-------------------------------------------------------------------------*/
393 addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
394 addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
395 addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
396 addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
397 mtdcr(PLB0_ACR, addr);
400 addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
401 addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
402 addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
403 addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
404 mtdcr(PLB1_ACR, addr);
408 #endif /* defined(CONFIG_PCI) */
410 /*************************************************************************
413 * The bootstrap configuration provides default settings for the pci
414 * inbound map (PIM). But the bootstrap config choices are limited and
415 * may not be sufficient for a given board.
417 ************************************************************************/
418 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
419 void pci_target_init(struct pci_controller *hose)
421 /*--------------------------------------------------------------------------+
422 * Set up Direct MMIO registers
423 *--------------------------------------------------------------------------*/
424 /*--------------------------------------------------------------------------+
425 | PowerPC440 EP PCI Master configuration.
426 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
427 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
428 | Use byte reversed out routines to handle endianess.
429 | Make this region non-prefetchable.
430 +--------------------------------------------------------------------------*/
431 out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
432 out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
433 out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
434 out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
435 out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
437 out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
438 out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
439 out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
440 out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
441 out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
443 out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
444 out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
445 out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
446 out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
448 /*--------------------------------------------------------------------------+
449 * Set up Configuration registers
450 *--------------------------------------------------------------------------*/
452 /* Program the board's subsystem id/vendor id */
453 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
454 CONFIG_SYS_PCI_SUBSYS_VENDORID);
455 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
457 /* Configure command register as bus master */
458 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
460 /* 240nS PCI clock */
461 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
463 /* No error reporting */
464 pci_write_config_word(0, PCI_ERREN, 0);
466 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
469 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
471 /*************************************************************************
474 ************************************************************************/
475 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
476 void pci_master_init(struct pci_controller *hose)
478 unsigned short temp_short;
480 /*--------------------------------------------------------------------------+
481 | Write the PowerPC440 EP PCI Configuration regs.
482 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
483 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
484 +--------------------------------------------------------------------------*/
485 pci_read_config_word(0, PCI_COMMAND, &temp_short);
486 pci_write_config_word(0, PCI_COMMAND,
487 temp_short | PCI_COMMAND_MASTER |
490 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
492 /*************************************************************************
495 * This routine is called to reset (keep alive) the watchdog timer
497 ************************************************************************/
498 #if defined(CONFIG_HW_WATCHDOG)
499 void hw_watchdog_reset(void)
505 void board_reset(void)
507 /* give reset to BCSR */
508 *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09;