3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #include <asm/processor.h>
25 /*************************************************************************
27 * initdram -- 440EPx's DDR controller is a DENALI Core
29 ************************************************************************/
30 long int initdram (int board_type)
32 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
35 mtsdram(DDR0_02, 0x00000000);
37 mtsdram(DDR0_00, 0x0000190A);
38 mtsdram(DDR0_01, 0x01000000);
39 mtsdram(DDR0_03, 0x02030602);
40 mtsdram(DDR0_04, 0x13030300);
41 mtsdram(DDR0_05, 0x0202050E);
42 mtsdram(DDR0_06, 0x0104C823);
43 mtsdram(DDR0_07, 0x000D0100);
44 mtsdram(DDR0_08, 0x02360001);
45 mtsdram(DDR0_09, 0x00011D5F);
46 mtsdram(DDR0_10, 0x00000300);
47 mtsdram(DDR0_11, 0x0027C800);
48 mtsdram(DDR0_12, 0x00000003);
49 mtsdram(DDR0_14, 0x00000000);
50 mtsdram(DDR0_17, 0x19000000);
51 mtsdram(DDR0_18, 0x19191919);
52 mtsdram(DDR0_19, 0x19191919);
53 mtsdram(DDR0_20, 0x0B0B0B0B);
54 mtsdram(DDR0_21, 0x0B0B0B0B);
55 mtsdram(DDR0_22, 0x00267F0B);
56 mtsdram(DDR0_23, 0x00000000);
57 mtsdram(DDR0_24, 0x01010002);
58 mtsdram(DDR0_26, 0x5B260181);
59 mtsdram(DDR0_27, 0x0000682B);
60 mtsdram(DDR0_28, 0x00000000);
61 mtsdram(DDR0_31, 0x00000000);
62 mtsdram(DDR0_42, 0x01000006);
63 mtsdram(DDR0_43, 0x050A0200);
64 mtsdram(DDR0_44, 0x00000005);
65 mtsdram(DDR0_02, 0x00000001);
68 * Wait for DCC master delay line to finish calibration
70 mfsdram(DDR0_17, val);
71 while (((val >> 8) & 0x000007f) == 0) {
72 mfsdram(DDR0_17, val);
74 #endif /* #ifndef CONFIG_NAND_U_BOOT */
76 return (CFG_MBYTES_SDRAM << 20);