3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #include <ppc_asm.tmpl>
23 #include <asm-ppc/mmu.h>
26 /**************************************************************************
29 * This table is used by the cpu boot code to setup the initial tlb
30 * entries. Rather than make broad assumptions in the cpu source tree,
31 * this table lets each board set things up however they like.
33 * Pointer to the table is returned in r1
35 *************************************************************************/
43 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
44 * speed up boot process. It is patched after relocation to enable SA_I
46 #ifndef CONFIG_NAND_SPL
47 tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
49 tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
52 /* TLB-entry for DDR SDRAM (Up to 2GB) */
53 #ifdef CONFIG_4xx_DCACHE
54 tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
56 tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
59 #ifdef CFG_INIT_RAM_DCACHE
60 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
61 tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
64 /* TLB-entry for PCI Memory */
65 tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
66 tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
67 tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
68 tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
70 /* TLB-entry for EBC */
71 tlbentry( CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
73 /* TLB-entry for NAND */
74 tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
76 /* TLB-entry for Internal Registers & OCM */
77 tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
79 /*TLB-entry PCI registers*/
80 tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
82 /* TLB-entry for peripherals */
83 tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
85 /* TLB-entry PCI IO Space - from sr@denx.de */
86 tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
90 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
92 * For NAND booting the first TLB has to be reconfigured to full size
93 * and with caching disabled after running from RAM!
95 #define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
96 #define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1)
97 #define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
103 addi r4,r0,0x0000 /* TLB entry #0 */
106 tlbwe r5,r4,0x0000 /* Save it out */
109 tlbwe r5,r4,0x0001 /* Save it out */
112 tlbwe r5,r4,0x0002 /* Save it out */