2 * Copyright (C) 2004 PaulReynolds@lhsolutions.com
5 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
30 #include <spd_sdram.h>
31 #include <ppc4xx_enet.h>
33 #define BOOT_SMALL_FLASH 32 /* 00100000 */
34 #define FLASH_ONBD_N 2 /* 00000010 */
35 #define FLASH_SRAM_SEL 1 /* 00000001 */
37 long int fixed_sdram (void);
38 void fpga_init (void);
40 int board_early_init_f (void)
43 unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
44 unsigned char switch_status;
45 unsigned long cs0_base;
46 unsigned long cs0_size;
47 unsigned long cs0_twt;
48 unsigned long cs2_base;
49 unsigned long cs2_size;
50 unsigned long cs2_twt;
52 /*-------------------------------------------------------------------------+
53 | Initialize EBC CONFIG
54 +-------------------------------------------------------------------------*/
55 mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
56 EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
57 EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
58 EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
59 EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
61 /*-------------------------------------------------------------------------+
62 | FPGA. Initialize bank 7 with default values.
63 +-------------------------------------------------------------------------*/
64 mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
66 EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
67 EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
68 EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
69 EBC_BXAP_BEM_WRITEONLY|
70 EBC_BXAP_PEN_DISABLED);
71 mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
72 EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
74 /* read FPGA base register FPGA_REG0 */
75 switch_status = *fpga_base;
77 if (switch_status & 0x40) {
78 cs0_base = 0xFFE00000;
79 cs0_size = EBC_BXCR_BS_2MB;
81 cs2_base = 0xFF800000;
82 cs2_size = EBC_BXCR_BS_4MB;
85 cs0_base = 0xFFC00000;
86 cs0_size = EBC_BXCR_BS_4MB;
88 cs2_base = 0xFF800000;
89 cs2_size = EBC_BXCR_BS_2MB;
93 /*-------------------------------------------------------------------------+
94 | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
95 +-------------------------------------------------------------------------*/
96 mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
98 EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
99 EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
100 EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
101 EBC_BXAP_BEM_WRITEONLY|
102 EBC_BXAP_PEN_DISABLED);
103 mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
104 cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
106 /*-------------------------------------------------------------------------+
107 | 8KB NVRAM/RTC. Initialize bank 1 with default values.
108 +-------------------------------------------------------------------------*/
109 mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
110 EBC_BXAP_BCE_DISABLE|
111 EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
112 EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
113 EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
114 EBC_BXAP_BEM_WRITEONLY|
115 EBC_BXAP_PEN_DISABLED);
116 mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)|
117 EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
119 /*-------------------------------------------------------------------------+
120 | 4 MB FLASH. Initialize bank 2 with default values.
121 +-------------------------------------------------------------------------*/
122 mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
123 EBC_BXAP_BCE_DISABLE|
124 EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
125 EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
126 EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
127 EBC_BXAP_BEM_WRITEONLY|
128 EBC_BXAP_PEN_DISABLED);
129 mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
130 cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
132 /*-------------------------------------------------------------------------+
133 | FPGA. Initialize bank 7 with default values.
134 +-------------------------------------------------------------------------*/
135 mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
136 EBC_BXAP_BCE_DISABLE|
137 EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
138 EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
139 EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
140 EBC_BXAP_BEM_WRITEONLY|
141 EBC_BXAP_PEN_DISABLED);
142 mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
143 EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
145 /*--------------------------------------------------------------------
146 * Setup the interrupt controller polarities, triggers, etc.
147 *-------------------------------------------------------------------*/
148 mtdcr (uic0sr, 0xffffffff); /* clear all */
149 mtdcr (uic0er, 0x00000000); /* disable all */
150 mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
151 mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
152 mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
153 mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
154 mtdcr (uic0sr, 0xffffffff); /* clear all */
156 mtdcr (uic1sr, 0xffffffff); /* clear all */
157 mtdcr (uic1er, 0x00000000); /* disable all */
158 mtdcr (uic1cr, 0x00000000); /* all non-critical */
159 mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
160 mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
161 mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
162 mtdcr (uic1sr, 0xffffffff); /* clear all */
164 mtdcr (uic2sr, 0xffffffff); /* clear all */
165 mtdcr (uic2er, 0x00000000); /* disable all */
166 mtdcr (uic2cr, 0x00000000); /* all non-critical */
167 mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
168 mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
169 mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
170 mtdcr (uic2sr, 0xffffffff); /* clear all */
172 mtdcr (uicb0sr, 0xfc000000); /* clear all */
173 mtdcr (uicb0er, 0x00000000); /* disable all */
174 mtdcr (uicb0cr, 0x00000000); /* all non-critical */
175 mtdcr (uicb0pr, 0xfc000000); /* */
176 mtdcr (uicb0tr, 0x00000000); /* */
177 mtdcr (uicb0vr, 0x00000001); /* */
178 mfsdr (sdr_mfr, mfr);
179 mfr &= ~SDR0_MFR_ECS_MASK;
180 /* mtsdr(sdr_mfr, mfr); */
187 int checkboard (void)
190 unsigned char *s = getenv ("serial#");
192 get_sys_info (&sysinfo);
194 printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
201 printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
202 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
203 printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
204 printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
205 printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
210 long int initdram (int board_type)
214 #if defined(CONFIG_SPD_EEPROM)
215 dram_size = spd_sdram (0);
217 dram_size = fixed_sdram ();
223 #if defined(CFG_DRAM_TEST)
226 uint *pstart = (uint *) 0x00000000;
227 uint *pend = (uint *) 0x08000000;
230 for (p = pstart; p < pend; p++)
233 for (p = pstart; p < pend; p++) {
234 if (*p != 0xaaaaaaaa) {
235 printf ("SDRAM test fails at: %08x\n", (uint) p);
240 for (p = pstart; p < pend; p++)
243 for (p = pstart; p < pend; p++) {
244 if (*p != 0x55555555) {
245 printf ("SDRAM test fails at: %08x\n", (uint) p);
253 #if !defined(CONFIG_SPD_EEPROM)
254 /*************************************************************************
255 * fixed sdram init -- doesn't use serial presence detect.
257 * Assumes: 128 MB, non-ECC, non-registered
260 ************************************************************************/
261 long int fixed_sdram (void)
265 /*--------------------------------------------------------------------
267 *------------------------------------------------------------------*/
268 mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
269 mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
270 mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
271 mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
272 mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
274 /*--------------------------------------------------------------------
275 * Setup for board-specific specific mem
276 *------------------------------------------------------------------*/
278 * Following for CAS Latency = 2.5 @ 133 MHz PLB
280 mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
281 mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
283 mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
284 mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
285 mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
286 udelay (400); /* Delay 200 usecs (min) */
288 /*--------------------------------------------------------------------
289 * Enable the controller, then wait for DCEN to complete
290 *------------------------------------------------------------------*/
291 mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
293 mfsdram (mem_mcsts, reg);
294 if (reg & 0x80000000)
298 return (128 * 1024 * 1024); /* 128 MB */
300 #endif /* !defined(CONFIG_SPD_EEPROM) */
303 /*************************************************************************
306 * This routine is called just prior to registering the hose and gives
307 * the board the opportunity to check things. Returning a value of zero
308 * indicates that things are bad & PCI initialization should be aborted.
310 * Different boards may wish to customize the pci controller structure
311 * (add regions, override default access routines, etc) or perform
312 * certain pre-initialization actions.
314 ************************************************************************/
315 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
316 int pci_pre_init(struct pci_controller * hose )
320 /*--------------------------------------------------------------------------+
321 * The ocotea board is always configured as the host & requires the
322 * PCI arbiter to be enabled.
323 *--------------------------------------------------------------------------*/
324 mfsdr(sdr_sdstp1, strap);
325 if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
326 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
332 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
334 /*************************************************************************
337 * The bootstrap configuration provides default settings for the pci
338 * inbound map (PIM). But the bootstrap config choices are limited and
339 * may not be sufficient for a given board.
341 ************************************************************************/
342 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
343 void pci_target_init(struct pci_controller * hose )
345 DECLARE_GLOBAL_DATA_PTR;
347 /*--------------------------------------------------------------------------+
349 *--------------------------------------------------------------------------*/
350 out32r( PCIX0_PIM0SA, 0 ); /* disable */
351 out32r( PCIX0_PIM1SA, 0 ); /* disable */
352 out32r( PCIX0_PIM2SA, 0 ); /* disable */
353 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
355 /*--------------------------------------------------------------------------+
356 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
357 * options to not support sizes such as 128/256 MB.
358 *--------------------------------------------------------------------------*/
359 out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
360 out32r( PCIX0_PIM0LAH, 0 );
361 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
363 out32r( PCIX0_BAR0, 0 );
365 /*--------------------------------------------------------------------------+
366 * Program the board's subsystem id/vendor id
367 *--------------------------------------------------------------------------*/
368 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
369 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
371 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
373 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
376 /*************************************************************************
379 * This routine is called to determine if a pci scan should be
380 * performed. With various hardware environments (especially cPCI and
381 * PPMC) it's insufficient to depend on the state of the arbiter enable
382 * bit in the strap register, or generic host/adapter assumptions.
384 * Rather than hard-code a bad assumption in the general 440 code, the
385 * 440 pci code requires the board to decide at runtime.
387 * Return 0 for adapter mode, non-zero for host (monarch) mode.
390 ************************************************************************/
391 #if defined(CONFIG_PCI)
392 int is_pci_host(struct pci_controller *hose)
394 /* The ocotea board is always configured as host. */
397 #endif /* defined(CONFIG_PCI) */
403 unsigned long sdr0_pfc0;
404 unsigned long sdr0_pfc1;
405 unsigned long sdr0_cust0;
408 mfsdr (sdr_pfc0, sdr0_pfc0);
409 mfsdr (sdr_pfc1, sdr0_pfc1);
410 group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
413 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
414 if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
415 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
416 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
417 out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
418 FPGA_REG2_EXT_INTFACE_ENABLE);
419 mtsdr (sdr_pfc0, sdr0_pfc0);
420 mtsdr (sdr_pfc1, sdr0_pfc1);
422 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
429 out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
430 FPGA_REG2_EXT_INTFACE_ENABLE);
431 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
432 mtsdr (sdr_pfc0, sdr0_pfc0);
433 mtsdr (sdr_pfc1, sdr0_pfc1);
439 /* CPU trace B - Over EBMI */
440 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
441 mtsdr (sdr_pfc0, sdr0_pfc0);
442 mtsdr (sdr_pfc1, sdr0_pfc1);
443 out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
444 FPGA_REG2_EXT_INTFACE_DISABLE);
449 /* Initialize the ethernet specific functions in the fpga */
450 mfsdr(sdr_pfc1, sdr0_pfc1);
451 mfsdr(sdr_cust0, sdr0_cust0);
452 if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
453 ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
454 (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
456 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
458 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
459 FPGA_REG3_ENET_GROUP7);
463 if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
465 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
466 FPGA_REG3_ENET_GROUP7);
470 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
471 FPGA_REG3_ENET_GROUP8);
477 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
479 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
480 FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
484 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
485 FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
488 out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
489 FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
490 FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
492 /* reset the gigabyte phy if necessary */
493 if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
495 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
497 out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
499 out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
503 out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
505 out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
509 /* Turn off the LED's */
510 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
511 FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
512 FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
519 * Returns 1 if keys pressed to start the power-on long-running tests
520 * Called from board_init_f().
522 int post_hotkeys_pressed(void)