3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
32 long int initdram(int board_type)
35 * Same as on Kilauea, Makalu generates exception 0x200
36 * (machine check) after trap_init() in board_init_f,
37 * when SDRAM is initialized here (late) and d-cache is
38 * used earlier as INIT_RAM.
39 * So for now, initialize DDR2 in init.S very early and
40 * also use it for INIT_RAM. Then this exception doesn't
46 /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
47 mtsdram(SDRAM_MB0CF, 0x00005201);
49 /* SET SDRAM_MB1CF - Not enabled */
50 mtsdram(SDRAM_MB1CF, 0x00000000);
52 /* SET SDRAM_MB2CF - Not enabled */
53 mtsdram(SDRAM_MB2CF, 0x00000000);
55 /* SET SDRAM_MB3CF - Not enabled */
56 mtsdram(SDRAM_MB3CF, 0x00000000);
58 /* SDRAM_CLKTR: Adv Addr clock by 90 deg */
59 mtsdram(SDRAM_CLKTR, 0x80000000);
61 /* Refresh Time register (0x30) Refresh every 7.8125uS */
62 mtsdram(SDRAM_RTR, 0x06180000);
65 mtsdram(SDRAM_SDTR1, 0x80201000);
68 mtsdram(SDRAM_SDTR2, 0x32204232);
71 mtsdram(SDRAM_SDTR3, 0x080b0d1a);
73 mtsdram(SDRAM_MMODE, 0x00000442);
74 mtsdram(SDRAM_MEMODE, 0x00000404);
76 /* SDRAM0_MCOPT1 (0X20) No ECC Gen */
77 mtsdram(SDRAM_MCOPT1, 0x04322000);
80 mtsdram(SDRAM_INITPLR0, 0xa8380000);
81 /* precharge 3 DDR clock cycle */
82 mtsdram(SDRAM_INITPLR1, 0x81900400);
84 mtsdram(SDRAM_INITPLR2, 0x81020000);
86 mtsdram(SDRAM_INITPLR3, 0x81030000);
87 /* EMR DLL ENABLE twr = 2tck */
88 mtsdram(SDRAM_INITPLR4, 0x81010404);
90 * Note: 5 is CL. May need to be changed
92 mtsdram(SDRAM_INITPLR5, 0x81000542);
93 /* precharge 3 DDR clock cycle */
94 mtsdram(SDRAM_INITPLR6, 0x81900400);
95 /* Auto-refresh trfc = 26tck */
96 mtsdram(SDRAM_INITPLR7, 0x8D080000);
97 /* Auto-refresh trfc = 26tck */
98 mtsdram(SDRAM_INITPLR8, 0x8D080000);
100 mtsdram(SDRAM_INITPLR9, 0x8D080000);
102 mtsdram(SDRAM_INITPLR10, 0x8D080000);
103 /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
104 mtsdram(SDRAM_INITPLR11, 0x81000442);
105 mtsdram(SDRAM_INITPLR12, 0x81010780);
106 mtsdram(SDRAM_INITPLR13, 0x81010400);
107 mtsdram(SDRAM_INITPLR14, 0x00000000);
108 mtsdram(SDRAM_INITPLR15, 0x00000000);
110 /* SET MCIF0_CODT Die Termination On */
111 mtsdram(SDRAM_CODT, 0x0080f837);
112 mtsdram(SDRAM_MODT0, 0x01800000);
113 mtsdram(SDRAM_MODT1, 0x00000000);
115 mtsdram(SDRAM_WRDTR, 0x00000000);
117 /* SDRAM0_MCOPT2 (0X21) Start initialization */
118 mtsdram(SDRAM_MCOPT2, 0x20000000);
122 mfsdram(SDRAM_MCSTAT, val);
123 } while ((val & SDRAM_MCSTAT_MIC_COMP) != SDRAM_MCSTAT_MIC_COMP);
128 mtsdram(SDRAM_DLCR, 0x030000a5);
131 mtsdram(SDRAM_RDCC, 0x40000000);
134 mtsdram(SDRAM_RQDC, 0x80000038);
137 mtsdram(SDRAM_RFDC, 0x00000209);
139 /* Enable memory controller */
140 mfsdram(SDRAM_MCOPT2, val);
141 val |= SDRAM_MCOPT2_DCEN_ENABLE;
142 mtsdram(SDRAM_MCOPT2, val);
144 return (CFG_MBYTES_SDRAM << 20);
147 #if defined(CFG_DRAM_TEST)
150 printf ("testdram\n");
151 #if defined (CONFIG_NAND_U_BOOT)
154 uint *pstart = (uint *) 0x00000000;
155 uint *pend = (uint *) 0x00001000;
158 for (p = pstart; p < pend; p++) {
162 for (p = pstart; p < pend; p++) {
163 if (*p != 0xaaaaaaaa) {
164 #if !defined (CONFIG_NAND_SPL)
165 printf ("SDRAM test fails at: %08x\n", (uint) p);
171 for (p = pstart; p < pend; p++) {
175 for (p = pstart; p < pend; p++) {
176 if (*p != 0x55555555) {
177 #if !defined (CONFIG_NAND_SPL)
178 printf ("SDRAM test fails at: %08x\n", (uint) p);
183 #if !defined (CONFIG_NAND_SPL)
184 printf ("SDRAM test passed!!!\n");