3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
29 #include <asm-ppc/io.h>
32 #include "../cpu/ppc4xx/440spe_pcie.h"
35 /* #define PCIE_ENDPOINT 1 */
37 int ppc440spe_init_pcie_rootport(int port);
38 void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
40 int board_early_init_f (void)
45 /*----------------------------------------------------------------------+
46 * Interrupt controller setup for the Katmai 440SPe Evaluation board.
47 *-----------------------------------------------------------------------+
48 *-----------------------------------------------------------------------+
49 * Interrupt | Source | Pol. | Sensi.| Crit. |
50 *-----------+-----------------------------------+-------+-------+-------+
51 * IRQ 00 | UART0 | High | Level | Non |
52 * IRQ 01 | UART1 | High | Level | Non |
53 * IRQ 02 | IIC0 | High | Level | Non |
54 * IRQ 03 | IIC1 | High | Level | Non |
55 * IRQ 04 | PCI0X0 MSG IN | High | Level | Non |
56 * IRQ 05 | PCI0X0 CMD Write | High | Level | Non |
57 * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non |
58 * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non |
59 * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non |
60 * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non |
61 * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non |
62 * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit |
63 * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non |
64 * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non |
65 * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non |
66 * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non |
67 * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non |
68 * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit |
69 * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non |
70 * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non |
71 * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non |
72 * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non |
73 * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non |
74 * IRQ 23 | I2O Inbound Doorbell | High | Level | Non |
75 * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non |
76 * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non |
77 * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non |
78 * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non |
79 * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non |
80 * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non |
81 * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non |
82 * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. |
83 *------------------------------------------------------------------------
84 * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non |
85 * IRQ 33 | MAL Serr | High | Level | Non |
86 * IRQ 34 | MAL Txde | High | Level | Non |
87 * IRQ 35 | MAL Rxde | High | Level | Non |
88 * IRQ 36 | DMC CE or DMC UE | High | Level | Non |
89 * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non |
90 * IRQ 38 | MAL TX EOB | High | Level | Non |
91 * IRQ 39 | MAL RX EOB | High | Level | Non |
92 * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non |
93 * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non |
94 * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non |
95 * IRQ 43 | L2 Cache | Risin | Edge | Non |
96 * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non |
97 * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non |
98 * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non |
99 * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non |
100 * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non |
101 * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non |
102 * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non |
103 * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non |
104 * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non |
105 * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non |
106 * IRQ 54 | DMA Error | High | Level | Non |
107 * IRQ 55 | DMA I2O Error | High | Level | Non |
108 * IRQ 56 | Serial ROM | High | Level | Non |
109 * IRQ 57 | PCIX0 Error | High | Edge | Non |
110 * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non |
111 * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non |
112 * IRQ 60 | EMAC0 Interrupt | High | Level | Non |
113 * IRQ 61 | EMAC0 Wake-up | High | Level | Non |
114 * IRQ 62 | Reserved | High | Level | Non |
115 * IRQ 63 | XOR | High | Level | Non |
116 *-----------------------------------------------------------------------
117 * IRQ 64 | PE0 AL | High | Level | Non |
118 * IRQ 65 | PE0 VPD Access | Risin | Edge | Non |
119 * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non |
120 * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non |
121 * IRQ 68 | PE0 TCR | High | Level | Non |
122 * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non |
123 * IRQ 70 | PE0 DCR Error | High | Level | Non |
124 * IRQ 71 | Reserved | N/A | N/A | Non |
125 * IRQ 72 | PE1 AL | High | Level | Non |
126 * IRQ 73 | PE1 VPD Access | Risin | Edge | Non |
127 * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non |
128 * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non |
129 * IRQ 76 | PE1 TCR | High | Level | Non |
130 * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non |
131 * IRQ 78 | PE1 DCR Error | High | Level | Non |
132 * IRQ 79 | Reserved | N/A | N/A | Non |
133 * IRQ 80 | PE2 AL | High | Level | Non |
134 * IRQ 81 | PE2 VPD Access | Risin | Edge | Non |
135 * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non |
136 * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non |
137 * IRQ 84 | PE2 TCR | High | Level | Non |
138 * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non |
139 * IRQ 86 | PE2 DCR Error | High | Level | Non |
140 * IRQ 87 | Reserved | N/A | N/A | Non |
141 * IRQ 88 | External IRQ(5) | Progr | Progr | Non |
142 * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non |
143 * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non |
144 * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non |
145 * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non |
146 * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non |
147 * IRQ 94 | Reserved | N/A | N/A | Non |
148 * IRQ 95 | Reserved | N/A | N/A | Non |
149 *-----------------------------------------------------------------------
150 * IRQ 96 | PE0 INTA | High | Level | Non |
151 * IRQ 97 | PE0 INTB | High | Level | Non |
152 * IRQ 98 | PE0 INTC | High | Level | Non |
153 * IRQ 99 | PE0 INTD | High | Level | Non |
154 * IRQ 100 | PE1 INTA | High | Level | Non |
155 * IRQ 101 | PE1 INTB | High | Level | Non |
156 * IRQ 102 | PE1 INTC | High | Level | Non |
157 * IRQ 103 | PE1 INTD | High | Level | Non |
158 * IRQ 104 | PE2 INTA | High | Level | Non |
159 * IRQ 105 | PE2 INTB | High | Level | Non |
160 * IRQ 106 | PE2 INTC | High | Level | Non |
161 * IRQ 107 | PE2 INTD | Risin | Edge | Non |
162 * IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non |
163 * IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non |
164 * IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non |
165 * IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non |
166 * IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non |
167 * IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non |
168 * IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non |
169 * IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non |
170 * IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non |
171 * IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non |
172 * IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non |
173 * IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non |
174 * IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non |
175 * IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non |
176 * IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non |
177 * IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non |
178 * IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non |
179 * IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non |
180 * IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non |
181 * IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non |
182 *-----------+-----------------------------------+-------+-------+-------+ */
183 /*-------------------------------------------------------------------------+
184 * Put UICs in PowerPC440SPemode.
185 * Initialise UIC registers. Clear all interrupts. Disable all interrupts.
186 * Set critical interrupt values. Set interrupt polarities. Set interrupt
187 * trigger levels. Make bit 0 High priority. Clear all interrupts again.
188 *------------------------------------------------------------------------*/
189 mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */
190 mtdcr (uic3er, 0x00000000); /* disable all interrupts */
191 mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical interrupts: */
192 mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities*/
193 mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
194 mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
195 mtdcr (uic3sr, 0x00000000); /* clear all interrupts*/
196 mtdcr (uic3sr, 0xffffffff); /* clear all interrupts*/
199 mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
200 mtdcr (uic2er, 0x00000000); /* disable all interrupts*/
201 mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
202 mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities*/
203 mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
204 mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
205 mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
206 mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
208 mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts*/
209 mtdcr (uic1er, 0x00000000); /* disable all interrupts*/
210 mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts*/
211 mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */
212 mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels*/
213 mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
214 mtdcr (uic1sr, 0x00000000); /* clear all interrupts*/
215 mtdcr (uic1sr, 0xffffffff); /* clear all interrupts*/
217 mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
218 mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted cascade to be checked */
219 mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical interrupts*/
220 mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities*/
221 mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */
222 mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
223 mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/
224 mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/
226 /* SDR0_MFR should be part of Ethernet init */
227 mfsdr (sdr_mfr, mfr);
228 mfr &= ~SDR0_MFR_ECS_MASK;
229 /* mtsdr(sdr_mfr, mfr); */
232 * Setup GPIO signalling per defines in katmai.h
235 mtsdr(SDR0_PFC0, pfc);
237 out32(GPIO0_OR_ADDR, GPIO_OR_KATMAI);
238 out32(GPIO0_ODR_ADDR, GPIO_ODR_KATMAI);
239 out32(GPIO0_TCR_ADDR, GPIO_TCR_KATMAI);
244 int checkboard (void)
246 char *s = getenv("serial#");
248 printf("Board: Katmai - AMCC 440SPe Evaluation Board");
258 #if defined(CFG_DRAM_TEST)
261 uint *pstart = (uint *) 0x00000000;
262 uint *pend = (uint *) 0x08000000;
265 for (p = pstart; p < pend; p++)
268 for (p = pstart; p < pend; p++) {
269 if (*p != 0xaaaaaaaa) {
270 printf ("SDRAM test fails at: %08x\n", (uint) p);
275 for (p = pstart; p < pend; p++)
278 for (p = pstart; p < pend; p++) {
279 if (*p != 0x55555555) {
280 printf ("SDRAM test fails at: %08x\n", (uint) p);
288 /*************************************************************************
291 * This routine is called just prior to registering the hose and gives
292 * the board the opportunity to check things. Returning a value of zero
293 * indicates that things are bad & PCI initialization should be aborted.
295 * Different boards may wish to customize the pci controller structure
296 * (add regions, override default access routines, etc) or perform
297 * certain pre-initialization actions.
299 ************************************************************************/
300 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
301 int pci_pre_init(struct pci_controller * hose )
305 /*-------------------------------------------------------------------+
306 * The katmai board is always configured as the host & requires the
307 * PCI arbiter to be enabled.
308 *-------------------------------------------------------------------*/
309 mfsdr(sdr_sdstp1, strap);
310 if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
311 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
317 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
319 /*************************************************************************
322 * The bootstrap configuration provides default settings for the pci
323 * inbound map (PIM). But the bootstrap config choices are limited and
324 * may not be sufficient for a given board.
326 ************************************************************************/
327 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
328 void pci_target_init(struct pci_controller * hose )
330 DECLARE_GLOBAL_DATA_PTR;
332 /*-------------------------------------------------------------------+
334 *-------------------------------------------------------------------*/
335 out32r( PCIX0_PIM0SA, 0 ); /* disable */
336 out32r( PCIX0_PIM1SA, 0 ); /* disable */
337 out32r( PCIX0_PIM2SA, 0 ); /* disable */
338 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
340 /*-------------------------------------------------------------------+
341 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
342 * strapping options to not support sizes such as 128/256 MB.
343 *-------------------------------------------------------------------*/
344 out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
345 out32r( PCIX0_PIM0LAH, 0 );
346 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
347 out32r( PCIX0_BAR0, 0 );
349 /*-------------------------------------------------------------------+
350 * Program the board's subsystem id/vendor id
351 *-------------------------------------------------------------------*/
352 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
353 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
355 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
357 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
359 #if defined(CONFIG_PCI)
360 /*************************************************************************
363 * This routine is called to determine if a pci scan should be
364 * performed. With various hardware environments (especially cPCI and
365 * PPMC) it's insufficient to depend on the state of the arbiter enable
366 * bit in the strap register, or generic host/adapter assumptions.
368 * Rather than hard-code a bad assumption in the general 440 code, the
369 * 440 pci code requires the board to decide at runtime.
371 * Return 0 for adapter mode, non-zero for host (monarch) mode.
374 ************************************************************************/
375 int is_pci_host(struct pci_controller *hose)
377 /* The katmai board is always configured as host. */
381 static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
383 void pcie_setup_hoses(void)
385 struct pci_controller *hose;
389 * assume we're called after the PCIX hose is initialized, which takes
390 * bus ID 0 and therefore start numbering PCIe's from 1.
393 for (i = 0; i <= 2; i++) {
395 if (ppc440spe_init_pcie_endport(i)) {
397 if (ppc440spe_init_pcie_rootport(i)) {
399 printf("PCIE%d: initialization failed\n", i);
403 hose = &pcie_hose[i];
404 hose->first_busno = bus;
405 hose->last_busno = bus;
408 /* setup mem resource */
409 pci_set_region(hose->regions + 0,
410 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
411 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
415 hose->region_count = 1;
416 pci_register_hose(hose);
419 ppc440spe_setup_pcie_endpoint(hose, i);
421 * Reson for no scanning is endpoint can not generate
422 * upstream configuration accesses.
425 ppc440spe_setup_pcie_rootpoint(hose, i);
427 * Config access can only go down stream
429 hose->last_busno = pci_hose_scan(hose);
433 #endif /* defined(CONFIG_PCI) */
435 int misc_init_f (void)
438 #if defined(CONFIG_STRESS)
443 /* minimal init for PCIe */
444 #if 0 /* test-only: test endpoint at some time, for now rootpoint only */
445 /* pci express 0 Endpoint Mode */
446 mfsdr(SDR0_PE0DLPSET, reg);
447 reg &= (~0x00400000);
448 mtsdr(SDR0_PE0DLPSET, reg);
450 /* pci express 0 Rootpoint Mode */
451 mfsdr(SDR0_PE0DLPSET, reg);
453 mtsdr(SDR0_PE0DLPSET, reg);
455 /* pci express 1 Rootpoint Mode */
456 mfsdr(SDR0_PE1DLPSET, reg);
458 mtsdr(SDR0_PE1DLPSET, reg);
459 /* pci express 2 Rootpoint Mode */
460 mfsdr(SDR0_PE2DLPSET, reg);
462 mtsdr(SDR0_PE2DLPSET, reg);
464 #if defined(CONFIG_STRESS)
466 * All this setting done by linux only needed by stress an charac. test
468 * PCIe 1 Rootpoint PCIe2 Endpoint
469 * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level
471 for (i=0,disp=0; i<8; i++,disp+=3) {
472 mfsdr(SDR0_PE0HSSSET1L0+disp, reg);
474 mtsdr(SDR0_PE0HSSSET1L0+disp, reg);
477 /*PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
478 for (i=0,disp=0; i<4; i++,disp+=3) {
479 mfsdr(SDR0_PE1HSSSET1L0+disp, reg);
481 mtsdr(SDR0_PE1HSSSET1L0+disp, reg);
484 /*PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
485 for (i=0,disp=0; i<4; i++,disp+=3) {
486 mfsdr(SDR0_PE2HSSSET1L0+disp, reg);
488 mtsdr(SDR0_PE2HSSSET1L0+disp, reg);
492 mtsdr(SDR0_PE2UTLSET1, reg);
494 mtsdr(SDR0_PE2UTLSET2, reg);
495 /* pci express 1 Endpoint Mode */
497 mtsdr(SDR0_PE2DLPSET, reg);
499 mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
507 * Returns 1 if keys pressed to start the power-on long-running tests
508 * Called from board_init_f().
510 int post_hotkeys_pressed(void)