2 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
25 #include <spd_sdram.h>
27 #define BOOT_SMALL_FLASH 32 /* 00100000 */
28 #define FLASH_ONBD_N 2 /* 00000010 */
29 #define FLASH_SRAM_SEL 1 /* 00000001 */
31 long int fixed_sdram(void);
33 int board_early_init_f(void)
36 unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
39 /*--------------------------------------------------------------------
40 * Setup the external bus controller/chip selects
41 *-------------------------------------------------------------------*/
42 mtdcr(ebccfga, xbcfg);
44 mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
46 mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */
47 mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
48 mtebc(pb7ap, 0x01015280); /* FPGA registers */
49 mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
51 /* read FPGA_REG0 and set the bus controller */
53 if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
54 mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */
55 mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
56 mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */
57 mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
59 mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */
60 mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
62 /* set CS2 if FLASH_ONBD_N == 0 */
63 if (!(status & FLASH_ONBD_N)) {
64 mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */
65 mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
69 /*--------------------------------------------------------------------
70 * Setup the interrupt controller polarities, triggers, etc.
71 *-------------------------------------------------------------------*/
72 mtdcr(uic0sr, 0xffffffff); /* clear all */
73 mtdcr(uic0er, 0x00000000); /* disable all */
74 mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
75 mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
76 mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
77 mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
78 mtdcr(uic0sr, 0xffffffff); /* clear all */
80 mtdcr(uic1sr, 0xffffffff); /* clear all */
81 mtdcr(uic1er, 0x00000000); /* disable all */
82 mtdcr(uic1cr, 0x00000000); /* all non-critical */
83 mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
84 mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
85 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
86 mtdcr(uic1sr, 0xffffffff); /* clear all */
93 char *s = getenv("serial#");
95 printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
105 long int initdram(int board_type)
109 #if defined(CONFIG_SPD_EEPROM)
110 dram_size = spd_sdram(0);
112 dram_size = fixed_sdram();
117 #if defined(CFG_DRAM_TEST)
120 uint *pstart = (uint *) 0x00000000;
121 uint *pend = (uint *) 0x08000000;
124 for (p = pstart; p < pend; p++)
127 for (p = pstart; p < pend; p++) {
128 if (*p != 0xaaaaaaaa) {
129 printf("SDRAM test fails at: %08x\n", (uint) p);
134 for (p = pstart; p < pend; p++)
137 for (p = pstart; p < pend; p++) {
138 if (*p != 0x55555555) {
139 printf("SDRAM test fails at: %08x\n", (uint) p);
147 #if !defined(CONFIG_SPD_EEPROM)
148 /*************************************************************************
149 * fixed sdram init -- doesn't use serial presence detect.
151 * Assumes: 128 MB, non-ECC, non-registered
154 ************************************************************************/
155 long int fixed_sdram(void)
159 /*--------------------------------------------------------------------
161 *------------------------------------------------------------------*/
162 mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
163 mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
164 mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
165 mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
166 mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
168 /*--------------------------------------------------------------------
169 * Setup for board-specific specific mem
170 *------------------------------------------------------------------*/
172 * Following for CAS Latency = 2.5 @ 133 MHz PLB
174 mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
175 mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
177 mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
178 mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
179 mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
180 udelay(400); /* Delay 200 usecs (min) */
182 /*--------------------------------------------------------------------
183 * Enable the controller, then wait for DCEN to complete
184 *------------------------------------------------------------------*/
185 mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
187 mfsdram(mem_mcsts, reg);
188 if (reg & 0x80000000)
192 return (128 * 1024 * 1024); /* 128 MB */
194 #endif /* !defined(CONFIG_SPD_EEPROM) */
196 /*************************************************************************
199 * This routine is called just prior to registering the hose and gives
200 * the board the opportunity to check things. Returning a value of zero
201 * indicates that things are bad & PCI initialization should be aborted.
203 * Different boards may wish to customize the pci controller structure
204 * (add regions, override default access routines, etc) or perform
205 * certain pre-initialization actions.
207 ************************************************************************/
208 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
209 int pci_pre_init(struct pci_controller *hose)
213 /*--------------------------------------------------------------------------+
214 * The ebony board is always configured as the host & requires the
215 * PCI arbiter to be enabled.
216 *--------------------------------------------------------------------------*/
217 strap = mfdcr(cpc0_strp1);
218 if ((strap & 0x00100000) == 0) {
219 printf("PCI: CPC0_STRP1[PAE] not set.\n");
225 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
227 /*************************************************************************
230 * The bootstrap configuration provides default settings for the pci
231 * inbound map (PIM). But the bootstrap config choices are limited and
232 * may not be sufficient for a given board.
234 ************************************************************************/
235 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
236 void pci_target_init(struct pci_controller *hose)
238 DECLARE_GLOBAL_DATA_PTR;
240 /*--------------------------------------------------------------------------+
242 *--------------------------------------------------------------------------*/
243 out32r(PCIX0_PIM0SA, 0); /* disable */
244 out32r(PCIX0_PIM1SA, 0); /* disable */
245 out32r(PCIX0_PIM2SA, 0); /* disable */
246 out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
248 /*--------------------------------------------------------------------------+
249 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
250 * options to not support sizes such as 128/256 MB.
251 *--------------------------------------------------------------------------*/
252 out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
253 out32r(PCIX0_PIM0LAH, 0);
254 out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
256 out32r(PCIX0_BAR0, 0);
258 /*--------------------------------------------------------------------------+
259 * Program the board's subsystem id/vendor id
260 *--------------------------------------------------------------------------*/
261 out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
262 out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
264 out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
266 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
268 /*************************************************************************
271 * This routine is called to determine if a pci scan should be
272 * performed. With various hardware environments (especially cPCI and
273 * PPMC) it's insufficient to depend on the state of the arbiter enable
274 * bit in the strap register, or generic host/adapter assumptions.
276 * Rather than hard-code a bad assumption in the general 440 code, the
277 * 440 pci code requires the board to decide at runtime.
279 * Return 0 for adapter mode, non-zero for host (monarch) mode.
282 ************************************************************************/
283 #if defined(CONFIG_PCI)
284 int is_pci_host(struct pci_controller *hose)
286 /* The ebony board is always configured as host. */
289 #endif /* defined(CONFIG_PCI) */