3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <ppc_asm.tmpl>
26 #include <asm-ppc/mmu.h>
28 /**************************************************************************
31 * This table is used by the cpu boot code to setup the initial tlb
32 * entries. Rather than make broad assumptions in the cpu source tree,
33 * this table lets each board set things up however they like.
35 * Pointer to the table is returned in r1
37 *************************************************************************/
45 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
46 * use the speed up boot process. It is patched after relocation to
49 #ifndef CONFIG_NAND_SPL
50 tlbentry(CFG_BOOT_BASE_ADDR, SZ_16M, CFG_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
52 tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
53 tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
54 tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
58 * TLB entries for SDRAM are not needed on this platform.
59 * They are dynamically generated in the SPD DDR(2) detection
63 #ifdef CFG_INIT_RAM_DCACHE
64 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
65 tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
68 tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
69 tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
70 tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
72 tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
73 tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
74 tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
75 tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
77 /* PCIe UTL register */
78 tlbentry(CFG_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
80 /* TLB-entry for NAND */
81 tlbentry(CFG_NAND_ADDR, SZ_16M, CFG_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
83 /* TLB-entry for CPLD */
84 tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
86 /* TLB-entry for OCM */
87 tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
89 /* TLB-entry for Local Configuration registers => peripherals */
90 tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
92 /* AHB: Internal USB Peripherals (USB, SATA) */
93 tlbentry(CFG_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
97 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
99 * For NAND booting the first TLB has to be reconfigured to full size
100 * and with caching disabled after running from RAM!
102 #define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
103 #define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1)
104 #define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
110 addi r4,r0,0x0000 /* TLB entry #0 */
113 tlbwe r5,r4,0x0000 /* Save it out */
116 tlbwe r5,r4,0x0001 /* Save it out */
119 tlbwe r5,r4,0x0002 /* Save it out */