3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <fdt_support.h>
25 #include <asm/processor.h>
28 #include <asm/4xx_pcie.h>
31 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
33 DECLARE_GLOBAL_DATA_PTR;
35 int board_early_init_f(void)
39 /*------------------------------------------------------------------+
40 * Setup the interrupt controller polarities, triggers, etc.
41 *------------------------------------------------------------------*/
42 mtdcr(uic0sr, 0xffffffff); /* clear all */
43 mtdcr(uic0er, 0x00000000); /* disable all */
44 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
45 mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
46 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
47 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
48 mtdcr(uic0sr, 0xffffffff); /* clear all */
50 mtdcr(uic1sr, 0xffffffff); /* clear all */
51 mtdcr(uic1er, 0x00000000); /* disable all */
52 mtdcr(uic1cr, 0x00000000); /* all non-critical */
53 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
54 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
55 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
56 mtdcr(uic1sr, 0xffffffff); /* clear all */
58 mtdcr(uic2sr, 0xffffffff); /* clear all */
59 mtdcr(uic2er, 0x00000000); /* disable all */
60 mtdcr(uic2cr, 0x00000000); /* all non-critical */
61 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
62 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
63 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
64 mtdcr(uic2sr, 0xffffffff); /* clear all */
66 mtdcr(uic3sr, 0xffffffff); /* clear all */
67 mtdcr(uic3er, 0x00000000); /* disable all */
68 mtdcr(uic3cr, 0x00000000); /* all non-critical */
69 mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
70 mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
71 mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
72 mtdcr(uic3sr, 0xffffffff); /* clear all */
74 /* SDR Setting - enable NDFC */
75 mfsdr(SDR0_CUST0, sdr0_cust0);
76 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
77 SDR0_CUST0_NDFC_ENABLE |
78 SDR0_CUST0_NDFC_BW_8_BIT |
79 SDR0_CUST0_NDFC_ARE_MASK |
80 SDR0_CUST0_NDFC_BAC_ENCODE(3) |
81 (0x80000000 >> (28 + CFG_NAND_CS));
82 mtsdr(SDR0_CUST0, sdr0_cust0);
85 * Configure PFC (Pin Function Control) registers
88 mtsdr(SDR0_PFC1, 0x00040000);
90 /* Enable PCI host functionality in SDR0_PCI0 */
91 mtsdr(SDR0_PCI0, 0xe0000000);
93 /* Enable ethernet and take out of reset */
94 out_8((void *)CFG_BCSR_BASE + 6, 0);
96 /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
97 out_8((void *)CFG_BCSR_BASE + 5, 0);
99 /* Enable USB host & USB-OTG */
100 out_8((void *)CFG_BCSR_BASE + 7, 0);
102 mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
104 /* Setup PLB4-AHB bridge based on the system address map */
105 mtdcr(AHB_TOP, 0x8000004B);
106 mtdcr(AHB_BOT, 0x8000004B);
109 * Configure USB-STP pins as alternate and not GPIO
110 * It seems to be neccessary to configure the STP pins as GPIO
111 * input at powerup (perhaps while USB reset is asserted). So
112 * we configure those pins to their "real" function now.
114 gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
115 gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
120 int checkboard (void)
122 char *s = getenv("serial#");
125 if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA))
126 printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
128 printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
140 * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
141 * board specific values.
143 u32 ddr_wrdtr(u32 default_val) {
144 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
147 u32 ddr_clktr(u32 default_val) {
148 return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
151 #if defined(CONFIG_NAND_U_BOOT)
153 * NAND booting U-Boot version uses a fixed initialization, since the whole
154 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
157 long int initdram(int board_type)
159 return CFG_MBYTES_SDRAM << 20;
163 #if defined(CFG_DRAM_TEST)
166 unsigned long *mem = (unsigned long *)0;
167 const unsigned long kend = (1024 / sizeof(unsigned long));
172 for (k = 0; k < CFG_KBYTES_SDRAM;
173 ++k, mem += (1024 / sizeof(unsigned long))) {
174 if ((k & 1023) == 0) {
175 printf("%3d MB\r", k / 1024);
178 memset(mem, 0xaaaaaaaa, 1024);
179 for (n = 0; n < kend; ++n) {
180 if (mem[n] != 0xaaaaaaaa) {
181 printf("SDRAM test fails at: %08x\n",
187 memset(mem, 0x55555555, 1024);
188 for (n = 0; n < kend; ++n) {
189 if (mem[n] != 0x55555555) {
190 printf("SDRAM test fails at: %08x\n",
196 printf("SDRAM test passes\n");
201 /*************************************************************************
204 * The bootstrap configuration provides default settings for the pci
205 * inbound map (PIM). But the bootstrap config choices are limited and
206 * may not be sufficient for a given board.
208 ************************************************************************/
209 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
210 void pci_target_init(struct pci_controller * hose )
212 /*-------------------------------------------------------------------+
214 *-------------------------------------------------------------------*/
215 out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
216 out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
217 out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
218 out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
220 /*-------------------------------------------------------------------+
221 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
222 * strapping options to not support sizes such as 128/256 MB.
223 *-------------------------------------------------------------------*/
224 out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
225 out_le32((void *)PCIX0_PIM0LAH, 0);
226 out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
227 out_le32((void *)PCIX0_BAR0, 0);
229 /*-------------------------------------------------------------------+
230 * Program the board's subsystem id/vendor id
231 *-------------------------------------------------------------------*/
232 out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
233 out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
235 out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
237 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
239 #if defined(CONFIG_PCI)
243 * This routine is called to determine if a pci scan should be
244 * performed. With various hardware environments (especially cPCI and
245 * PPMC) it's insufficient to depend on the state of the arbiter enable
246 * bit in the strap register, or generic host/adapter assumptions.
248 * Rather than hard-code a bad assumption in the general 440 code, the
249 * 440 pci code requires the board to decide at runtime.
251 * Return 0 for adapter mode, non-zero for host (monarch) mode.
253 int is_pci_host(struct pci_controller *hose)
255 /* Board is always configured as host. */
259 static struct pci_controller pcie_hose[2] = {{0},{0}};
261 void pcie_setup_hoses(int busno)
263 struct pci_controller *hose;
270 * assume we're called after the PCIX hose is initialized, which takes
271 * bus ID 0 and therefore start numbering PCIe's from 1.
274 for (i = 0; i <= 1; i++) {
277 ret = ppc4xx_init_pcie_endport(i);
279 ret = ppc4xx_init_pcie_rootport(i);
281 printf("PCIE%d: initialization as %s failed\n", i,
282 is_end_point(i) ? "endpoint" : "root-complex");
286 hose = &pcie_hose[i];
287 hose->first_busno = bus;
288 hose->last_busno = bus;
289 hose->current_busno = bus;
291 /* setup mem resource */
292 pci_set_region(hose->regions + 0,
293 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
294 CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
297 hose->region_count = 1;
298 pci_register_hose(hose);
300 if (is_end_point(i)) {
301 ppc4xx_setup_pcie_endpoint(hose, i);
303 * Reson for no scanning is endpoint can not generate
304 * upstream configuration accesses.
307 ppc4xx_setup_pcie_rootpoint(hose, i);
308 env = getenv ("pciscandelay");
310 delay = simple_strtoul(env, NULL, 10);
312 printf("Warning, expect noticable delay before "
313 "PCIe scan due to 'pciscandelay' value!\n");
314 mdelay(delay * 1000);
318 * Config access can only go down stream
320 hose->last_busno = pci_hose_scan(hose);
321 bus = hose->last_busno + 1;
325 #endif /* CONFIG_PCI */
327 int board_early_init_r (void)
330 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
331 * boot EBC mapping only supports a maximum of 16MBytes
332 * (4.ff00.0000 - 4.ffff.ffff).
333 * To solve this problem, the FLASH has to get remapped to another
334 * EBC address which accepts bigger regions:
336 * 0xfc00.0000 -> 4.cc00.0000
339 /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
340 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
341 mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
343 mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
346 /* Remove TLB entry of boot EBC mapping */
347 remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);
349 /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
350 program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE,
354 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
355 * 0xfc00.0000 is possible
359 * Clear potential errors resulting from auto-calibration.
360 * If not done, then we could get an interrupt later on when
361 * exceptions are enabled.
363 set_mcsr(get_mcsr());
368 int misc_init_r(void)
374 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
375 * This is board specific, so let's do it here.
377 mfsdr(SDR0_ETH_CFG, eth_cfg);
378 /* disable SGMII mode */
379 eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
380 SDR0_ETH_CFG_SGMII1_ENABLE |
381 SDR0_ETH_CFG_SGMII0_ENABLE);
382 /* Set the for 2 RGMII mode */
383 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
384 eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
385 eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
386 mtsdr(SDR0_ETH_CFG, eth_cfg);
389 * The AHB Bridge core is held in reset after power-on or reset
392 mfsdr(SDR0_SRST1, sdr0_srst1);
393 sdr0_srst1 &= ~SDR0_SRST1_AHB;
394 mtsdr(SDR0_SRST1, sdr0_srst1);
399 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
400 void ft_board_setup(void *blob, bd_t *bd)
405 ft_cpu_setup(blob, bd);
407 /* Fixup NOR mapping */
408 val[0] = 0; /* chip select number */
409 val[1] = 0; /* always 0 */
410 val[2] = gd->bd->bi_flashstart;
411 val[3] = gd->bd->bi_flashsize;
412 rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
413 val, sizeof(val), 1);
415 printf("Unable to update property NOR mapping, err=%s\n",
418 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */