3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <fdt_support.h>
26 #include <asm/processor.h>
29 #include <asm/4xx_pcie.h>
32 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
34 DECLARE_GLOBAL_DATA_PTR;
36 #define CONFIG_SYS_BCSR3_PCIE 0x10
38 #define BOARD_CANYONLANDS_PCIE 1
39 #define BOARD_CANYONLANDS_SATA 2
40 #define BOARD_GLACIER 3
41 #define BOARD_ARCHES 4
43 #if defined(CONFIG_ARCHES)
45 * FPGA read/write helper macros
47 static inline int board_fpga_read(int offset)
51 data = in_8((void *)(CONFIG_SYS_FPGA_BASE + offset));
56 static inline void board_fpga_write(int offset, int data)
58 out_8((void *)(CONFIG_SYS_FPGA_BASE + offset), data);
62 * CPLD read/write helper macros
64 static inline int board_cpld_read(int offset)
68 out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
69 data = in_8((void *)(CONFIG_SYS_CPLD_DATA));
74 static inline void board_cpld_write(int offset, int data)
76 out_8((void *)(CONFIG_SYS_CPLD_ADDR), offset);
77 out_8((void *)(CONFIG_SYS_CPLD_DATA), data);
79 #endif /* defined(CONFIG_ARCHES) */
81 int board_early_init_f(void)
83 #if !defined(CONFIG_ARCHES)
89 * Setup the interrupt controller polarities, triggers, etc.
91 mtdcr(uic0sr, 0xffffffff); /* clear all */
92 mtdcr(uic0er, 0x00000000); /* disable all */
93 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
94 mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
95 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
96 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
97 mtdcr(uic0sr, 0xffffffff); /* clear all */
99 mtdcr(uic1sr, 0xffffffff); /* clear all */
100 mtdcr(uic1er, 0x00000000); /* disable all */
101 mtdcr(uic1cr, 0x00000000); /* all non-critical */
102 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
103 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
104 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
105 mtdcr(uic1sr, 0xffffffff); /* clear all */
107 mtdcr(uic2sr, 0xffffffff); /* clear all */
108 mtdcr(uic2er, 0x00000000); /* disable all */
109 mtdcr(uic2cr, 0x00000000); /* all non-critical */
110 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
111 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
112 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
113 mtdcr(uic2sr, 0xffffffff); /* clear all */
115 mtdcr(uic3sr, 0xffffffff); /* clear all */
116 mtdcr(uic3er, 0x00000000); /* disable all */
117 mtdcr(uic3cr, 0x00000000); /* all non-critical */
118 mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
119 mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
120 mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
121 mtdcr(uic3sr, 0xffffffff); /* clear all */
123 #if !defined(CONFIG_ARCHES)
124 /* SDR Setting - enable NDFC */
125 mfsdr(SDR0_CUST0, sdr0_cust0);
126 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
127 SDR0_CUST0_NDFC_ENABLE |
128 SDR0_CUST0_NDFC_BW_8_BIT |
129 SDR0_CUST0_NDFC_ARE_MASK |
130 SDR0_CUST0_NDFC_BAC_ENCODE(3) |
131 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
132 mtsdr(SDR0_CUST0, sdr0_cust0);
136 * Configure PFC (Pin Function Control) registers
139 mtsdr(SDR0_PFC1, 0x00040000);
141 /* Enable PCI host functionality in SDR0_PCI0 */
142 mtsdr(SDR0_PCI0, 0xe0000000);
144 #if !defined(CONFIG_ARCHES)
145 /* Enable ethernet and take out of reset */
146 out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
148 /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
149 out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
151 /* Enable USB host & USB-OTG */
152 out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
154 mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
156 /* Setup PLB4-AHB bridge based on the system address map */
157 mtdcr(AHB_TOP, 0x8000004B);
158 mtdcr(AHB_BOT, 0x8000004B);
160 if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
162 * Configure USB-STP pins as alternate and not GPIO
163 * It seems to be neccessary to configure the STP pins as GPIO
164 * input at powerup (perhaps while USB reset is asserted). So
165 * we configure those pins to their "real" function now.
167 gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
168 gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
175 #if !defined(CONFIG_ARCHES)
176 static void canyonlands_sata_init(int board_type)
180 if (board_type == BOARD_CANYONLANDS_SATA) {
181 /* Put SATA in reset */
182 SDR_WRITE(SDR0_SRST1, 0x00020001);
184 /* Set the phy for SATA, not PCI-E port 0 */
185 reg = SDR_READ(PESDR0_PHY_CTL_RST);
186 SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
187 reg = SDR_READ(PESDR0_L0CLK);
188 SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
189 SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
190 SDR_WRITE(PESDR0_L0DRV, 0x00000104);
192 /* Bring SATA out of reset */
193 SDR_WRITE(SDR0_SRST1, 0x00000000);
196 #endif /* !defined(CONFIG_ARCHES) */
198 int get_cpu_num(void)
200 int cpu = NA_OR_UNKNOWN_CPU;
202 #if defined(CONFIG_ARCHES)
205 cpu_num = board_fpga_read(0x3);
207 /* sanity check; assume cpu numbering starts and increments from 0 */
208 if ((cpu_num >= 0) && (cpu_num < CONFIG_BD_NUM_CPUS))
215 #if !defined(CONFIG_ARCHES)
218 char *s = getenv("serial#");
221 if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) {
222 printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
223 gd->board_type = BOARD_GLACIER;
225 printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
226 if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
227 gd->board_type = BOARD_CANYONLANDS_PCIE;
229 gd->board_type = BOARD_CANYONLANDS_SATA;
232 switch (gd->board_type) {
233 case BOARD_CANYONLANDS_PCIE:
238 case BOARD_CANYONLANDS_SATA:
239 puts(", 1*PCIe/1*SATA");
243 printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
251 canyonlands_sata_init(gd->board_type);
256 #else /* defined(CONFIG_ARCHES) */
260 char *s = getenv("serial#");
262 printf("Board: Arches - AMCC DUAL PPC460GT Reference Design\n");
263 printf(" Revision %02x.%02x ",
264 board_fpga_read(0x0), board_fpga_read(0x1));
266 gd->board_type = BOARD_ARCHES;
268 /* Only CPU0 has access to CPLD registers */
269 if (get_cpu_num() == 0) {
270 u8 cfg_sw = board_cpld_read(0x1);
271 printf("(FPGA=%02x, CPLD=%02x)\n",
272 board_fpga_read(0x2), board_cpld_read(0x0));
273 printf(" Configuration Switch %d%d%d%d\n",
274 ((cfg_sw >> 3) & 0x01),
275 ((cfg_sw >> 2) & 0x01),
276 ((cfg_sw >> 1) & 0x01),
277 ((cfg_sw >> 0) & 0x01));
279 printf("(FPGA=%02x, CPLD=xx)\n", board_fpga_read(0x2));
283 printf(" Serial# %s\n", s);
287 #endif /* !defined(CONFIG_ARCHES) */
290 * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
291 * board specific values.
293 u32 ddr_wrdtr(u32 default_val) {
294 return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
297 u32 ddr_clktr(u32 default_val) {
298 return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
301 #if defined(CONFIG_NAND_U_BOOT)
303 * NAND booting U-Boot version uses a fixed initialization, since the whole
304 * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
307 phys_size_t initdram(int board_type)
309 return CONFIG_SYS_MBYTES_SDRAM << 20;
316 * The bootstrap configuration provides default settings for the pci
317 * inbound map (PIM). But the bootstrap config choices are limited and
318 * may not be sufficient for a given board.
320 #if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
321 void pci_target_init(struct pci_controller * hose )
326 out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
327 out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
328 out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
329 out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
332 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
333 * strapping options to not support sizes such as 128/256 MB.
335 out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
336 out_le32((void *)PCIX0_PIM0LAH, 0);
337 out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
338 out_le32((void *)PCIX0_BAR0, 0);
341 * Program the board's subsystem id/vendor id
343 out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
344 out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
346 out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
348 #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
350 #if defined(CONFIG_PCI)
354 * This routine is called to determine if a pci scan should be
355 * performed. With various hardware environments (especially cPCI and
356 * PPMC) it's insufficient to depend on the state of the arbiter enable
357 * bit in the strap register, or generic host/adapter assumptions.
359 * Rather than hard-code a bad assumption in the general 440 code, the
360 * 440 pci code requires the board to decide at runtime.
362 * Return 0 for adapter mode, non-zero for host (monarch) mode.
364 int is_pci_host(struct pci_controller *hose)
366 /* Board is always configured as host. */
370 static struct pci_controller pcie_hose[2] = {{0},{0}};
372 void pcie_setup_hoses(int busno)
374 struct pci_controller *hose;
382 * assume we're called after the PCIX hose is initialized, which takes
383 * bus ID 0 and therefore start numbering PCIe's from 1.
388 * Canyonlands with SATA enabled has only one PCIe slot
391 if (gd->board_type == BOARD_CANYONLANDS_SATA)
396 for (i = start; i <= 1; i++) {
399 ret = ppc4xx_init_pcie_endport(i);
401 ret = ppc4xx_init_pcie_rootport(i);
403 printf("PCIE%d: initialization as %s failed\n", i,
404 is_end_point(i) ? "endpoint" : "root-complex");
408 hose = &pcie_hose[i];
409 hose->first_busno = bus;
410 hose->last_busno = bus;
411 hose->current_busno = bus;
413 /* setup mem resource */
414 pci_set_region(hose->regions + 0,
415 CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
416 CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
417 CONFIG_SYS_PCIE_MEMSIZE,
419 hose->region_count = 1;
420 pci_register_hose(hose);
422 if (is_end_point(i)) {
423 ppc4xx_setup_pcie_endpoint(hose, i);
425 * Reson for no scanning is endpoint can not generate
426 * upstream configuration accesses.
429 ppc4xx_setup_pcie_rootpoint(hose, i);
430 env = getenv ("pciscandelay");
432 delay = simple_strtoul(env, NULL, 10);
434 printf("Warning, expect noticable delay before "
435 "PCIe scan due to 'pciscandelay' value!\n");
436 mdelay(delay * 1000);
440 * Config access can only go down stream
442 hose->last_busno = pci_hose_scan(hose);
443 bus = hose->last_busno + 1;
447 #endif /* CONFIG_PCI */
449 int board_early_init_r (void)
452 * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
453 * boot EBC mapping only supports a maximum of 16MBytes
454 * (4.ff00.0000 - 4.ffff.ffff).
455 * To solve this problem, the FLASH has to get remapped to another
456 * EBC address which accepts bigger regions:
458 * 0xfc00.0000 -> 4.cc00.0000
461 /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
462 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
463 mtebc(pb3cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
465 mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
468 /* Remove TLB entry of boot EBC mapping */
469 remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
471 /* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
472 program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
476 * Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
477 * 0xfc00.0000 is possible
481 * Clear potential errors resulting from auto-calibration.
482 * If not done, then we could get an interrupt later on when
483 * exceptions are enabled.
485 set_mcsr(get_mcsr());
490 #if !defined(CONFIG_ARCHES)
491 int misc_init_r(void)
499 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
500 * This is board specific, so let's do it here.
502 mfsdr(SDR0_ETH_CFG, eth_cfg);
503 /* disable SGMII mode */
504 eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
505 SDR0_ETH_CFG_SGMII1_ENABLE |
506 SDR0_ETH_CFG_SGMII0_ENABLE);
507 /* Set the for 2 RGMII mode */
508 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
509 eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
510 if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
511 eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
513 eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
514 mtsdr(SDR0_ETH_CFG, eth_cfg);
517 * The AHB Bridge core is held in reset after power-on or reset
520 mfsdr(SDR0_SRST1, sdr0_srst1);
521 sdr0_srst1 &= ~SDR0_SRST1_AHB;
522 mtsdr(SDR0_SRST1, sdr0_srst1);
526 * Disable square wave output: Batterie will be drained
527 * quickly, when this output is not disabled
529 val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
531 i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
536 #else /* defined(CONFIG_ARCHES) */
538 int misc_init_r(void)
545 * Set EMAC mode/configuration (GMII, SGMII, RGMII...).
546 * This is board specific, so let's do it here.
549 /* enable SGMII mode */
550 eth_cfg |= (SDR0_ETH_CFG_SGMII0_ENABLE |
551 SDR0_ETH_CFG_SGMII1_ENABLE |
552 SDR0_ETH_CFG_SGMII2_ENABLE);
554 /* Set EMAC for MDIO */
555 eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
557 /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
558 eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
560 mtsdr(SDR0_ETH_CFG, eth_cfg);
562 /* reset all SGMII interfaces */
563 mfsdr(SDR0_SRST1, reg);
564 reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
565 mtsdr(SDR0_SRST1, reg);
566 mtsdr(SDR0_ETH_STS, 0xFFFFFFFF);
567 mtsdr(SDR0_SRST1, 0x00000000);
570 mfsdr(SDR0_ETH_PLL, eth_pll);
571 } while (!(eth_pll & SDR0_ETH_PLL_PLLLOCK));
575 #endif /* !defined(CONFIG_ARCHES) */
577 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
578 void ft_board_setup(void *blob, bd_t *bd)
583 ft_cpu_setup(blob, bd);
585 /* Fixup NOR mapping */
586 val[0] = 0; /* chip select number */
587 val[1] = 0; /* always 0 */
588 val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L; /* we fixed up this address */
589 val[3] = gd->bd->bi_flashsize;
590 rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
591 val, sizeof(val), 1);
593 printf("Unable to update property NOR mapping, err=%s\n",
597 if (gd->board_type == BOARD_CANYONLANDS_SATA) {
599 * When SATA is selected we need to disable the first PCIe
600 * node in the device tree, so that Linux doesn't initialize
603 fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status",
604 "disabled", sizeof("disabled"), 1);
607 if (gd->board_type == BOARD_CANYONLANDS_PCIE) {
609 * When PCIe is selected we need to disable the SATA
610 * node in the device tree, so that Linux doesn't initialize
613 fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status",
614 "disabled", sizeof("disabled"), 1);
617 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */