3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm-offsets.h>
11 #include <ppc_asm.tmpl>
15 /**************************************************************************
18 * This table is used by the cpu boot code to setup the initial tlb
19 * entries. Rather than make broad assumptions in the cpu source tree,
20 * this table lets each board set things up however they like.
22 * Pointer to the table is returned in r1
24 *************************************************************************/
32 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
33 * speed up boot process. It is patched after relocation to enable SA_I
35 #ifndef CONFIG_NAND_SPL
36 tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
38 tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G)
39 tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
42 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
43 tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
45 /* PCI base & peripherals */
46 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG)
48 tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I)
49 tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I)
52 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG)
53 tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG)
54 tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG)
55 tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG)
58 tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
62 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
64 * For NAND booting the first TLB has to be reconfigured to full size
65 * and with caching disabled after running from RAM!
67 #define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
68 #define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
69 #define TLB02 TLB2(AC_RWX | SA_IG)
75 addi r4,r0,0x0000 /* TLB entry #0 */
78 tlbwe r5,r4,0x0000 /* Save it out */
81 tlbwe r5,r4,0x0001 /* Save it out */
84 tlbwe r5,r4,0x0002 /* Save it out */