3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
27 #include <spd_sdram.h>
31 void ext_bus_cntlr_init(void);
32 void configure_ppc440ep_pins(void);
33 int is_nand_selected(void);
35 unsigned char cfg_simulate_spd_eeprom[128];
37 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
39 { /* GPIO Alternate1 Alternate2 Alternate3 */
42 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0 -> EBC_ADDR(7) DMA_REQ(2) */
43 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1 -> EBC_ADDR(6) DMA_ACK(2) */
44 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2 -> EBC_ADDR(5) DMA_EOT/TC(2) */
45 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3 -> EBC_ADDR(4) DMA_REQ(3) */
46 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4 -> EBC_ADDR(3) DMA_ACK(3) */
47 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
48 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6 -> EBC_CS_N(1) */
49 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7 -> EBC_CS_N(2) */
50 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8 -> EBC_CS_N(3) */
51 { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9 -> EBC_CS_N(4) */
52 { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
53 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
54 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
55 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
56 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
57 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
58 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
59 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
60 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
61 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
62 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
63 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
64 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
65 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
66 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
67 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
68 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 -> USB2D_RXVALID */
69 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ USB2D_RXERROR */
70 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 -> USB2D_TXVALID */
71 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA USB2D_PAD_SUSPNDM */
72 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK USB2D_XCVRSELECT */
73 { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ USB2D_TERMSELECT */
77 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0 -> USB2D_OPMODE0 */
78 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1 -> USB2D_OPMODE1 */
79 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2 -> UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT */
80 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3 -> UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN */
81 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4 -> UART0_8PIN_CTS_N UART3_SIN */
82 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5 -> UART0_RTS_N */
83 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6 -> UART0_DTR_N UART1_SOUT */
84 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7 -> UART0_RI_N UART1_SIN */
85 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8 -> UIC_IRQ(0) */
86 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9 -> UIC_IRQ(1) */
87 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
88 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
89 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4) DMA_ACK(1) */
90 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6) DMA_EOT/TC(1) */
91 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7) DMA_REQ(0) */
92 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8) DMA_ACK(0) */
93 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9) DMA_EOT/TC(0) */
94 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
95 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 -> | */
96 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 -> | */
97 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 -> | */
98 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 -> | */
99 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 -> | */
100 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 -> \ Can be unselected thru TraceSelect Bit */
101 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 -> / in PowerPC440EP Chip */
102 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 -> | */
103 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 -> | */
104 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 -> | */
105 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 -> | */
106 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 -> | */
107 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 -> | */
108 { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
113 /*----------------------------------------------------------------------------+
114 | EBC Devices Characteristics
115 | Peripheral Bank Access Parameters - EBC0_BnAP
116 | Peripheral Bank Configuration Register - EBC0_BnCR
117 +----------------------------------------------------------------------------*/
119 #define EBC0_BNAP_SMALL_FLASH \
120 EBC0_BNAP_BME_DISABLED | \
121 EBC0_BNAP_TWT_ENCODE(6) | \
122 EBC0_BNAP_CSN_ENCODE(0) | \
123 EBC0_BNAP_OEN_ENCODE(1) | \
124 EBC0_BNAP_WBN_ENCODE(1) | \
125 EBC0_BNAP_WBF_ENCODE(3) | \
126 EBC0_BNAP_TH_ENCODE(1) | \
127 EBC0_BNAP_RE_ENABLED | \
128 EBC0_BNAP_SOR_DELAYED | \
129 EBC0_BNAP_BEM_WRITEONLY | \
130 EBC0_BNAP_PEN_DISABLED
132 #define EBC0_BNCR_SMALL_FLASH_CS0 \
133 EBC0_BNCR_BAS_ENCODE(0xFFF00000) | \
138 #define EBC0_BNCR_SMALL_FLASH_CS4 \
139 EBC0_BNCR_BAS_ENCODE(0x87F00000) | \
144 /* Large Flash or SRAM */
145 #define EBC0_BNAP_LARGE_FLASH_OR_SRAM \
146 EBC0_BNAP_BME_DISABLED | \
147 EBC0_BNAP_TWT_ENCODE(8) | \
148 EBC0_BNAP_CSN_ENCODE(0) | \
149 EBC0_BNAP_OEN_ENCODE(1) | \
150 EBC0_BNAP_WBN_ENCODE(1) | \
151 EBC0_BNAP_WBF_ENCODE(1) | \
152 EBC0_BNAP_TH_ENCODE(2) | \
153 EBC0_BNAP_SOR_DELAYED | \
155 EBC0_BNAP_PEN_DISABLED
157 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0 \
158 EBC0_BNCR_BAS_ENCODE(0xFF800000) | \
164 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4 \
165 EBC0_BNCR_BAS_ENCODE(0x87800000) | \
171 #define EBC0_BNAP_NVRAM_FPGA \
172 EBC0_BNAP_BME_DISABLED | \
173 EBC0_BNAP_TWT_ENCODE(9) | \
174 EBC0_BNAP_CSN_ENCODE(0) | \
175 EBC0_BNAP_OEN_ENCODE(1) | \
176 EBC0_BNAP_WBN_ENCODE(1) | \
177 EBC0_BNAP_WBF_ENCODE(0) | \
178 EBC0_BNAP_TH_ENCODE(2) | \
179 EBC0_BNAP_RE_ENABLED | \
180 EBC0_BNAP_SOR_DELAYED | \
181 EBC0_BNAP_BEM_WRITEONLY | \
182 EBC0_BNAP_PEN_DISABLED
184 #define EBC0_BNCR_NVRAM_FPGA_CS5 \
185 EBC0_BNCR_BAS_ENCODE(0x80000000) | \
191 #define EBC0_BNAP_NAND_FLASH \
192 EBC0_BNAP_BME_DISABLED | \
193 EBC0_BNAP_TWT_ENCODE(3) | \
194 EBC0_BNAP_CSN_ENCODE(0) | \
195 EBC0_BNAP_OEN_ENCODE(0) | \
196 EBC0_BNAP_WBN_ENCODE(0) | \
197 EBC0_BNAP_WBF_ENCODE(0) | \
198 EBC0_BNAP_TH_ENCODE(1) | \
199 EBC0_BNAP_RE_ENABLED | \
200 EBC0_BNAP_SOR_NOT_DELAYED | \
202 EBC0_BNAP_PEN_DISABLED
205 #define EBC0_BNCR_NAND_FLASH_CS0 0xB8400000
208 #define EBC0_BNCR_NAND_FLASH_CS1 \
209 EBC0_BNCR_BAS_ENCODE(0x90000000) | \
214 #define EBC0_BNCR_NAND_FLASH_CS2 \
215 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
221 #define EBC0_BNCR_NAND_FLASH_CS3 \
222 EBC0_BNCR_BAS_ENCODE(0x94000000) | \
227 int board_early_init_f(void)
229 ext_bus_cntlr_init();
231 /*--------------------------------------------------------------------
232 * Setup the interrupt controller polarities, triggers, etc.
233 *-------------------------------------------------------------------*/
234 mtdcr(uic0sr, 0xffffffff); /* clear all */
235 mtdcr(uic0er, 0x00000000); /* disable all */
236 mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
237 mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
238 mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
239 mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
240 mtdcr(uic0sr, 0xffffffff); /* clear all */
242 mtdcr(uic1sr, 0xffffffff); /* clear all */
243 mtdcr(uic1er, 0x00000000); /* disable all */
244 mtdcr(uic1cr, 0x00000000); /* all non-critical */
245 mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
246 mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
247 mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
248 mtdcr(uic1sr, 0xffffffff); /* clear all */
250 /*--------------------------------------------------------------------
251 * Setup the GPIO pins
252 *-------------------------------------------------------------------*/
253 out32(GPIO0_OSRL, 0x00000400);
254 out32(GPIO0_OSRH, 0x00000000);
255 out32(GPIO0_TSRL, 0x00000400);
256 out32(GPIO0_TSRH, 0x00000000);
257 out32(GPIO0_ISR1L, 0x00000000);
258 out32(GPIO0_ISR1H, 0x00000000);
259 out32(GPIO0_ISR2L, 0x00000000);
260 out32(GPIO0_ISR2H, 0x00000000);
261 out32(GPIO0_ISR3L, 0x00000000);
262 out32(GPIO0_ISR3H, 0x00000000);
264 out32(GPIO1_OSRL, 0x0C380000);
265 out32(GPIO1_OSRH, 0x00000000);
266 out32(GPIO1_TSRL, 0x0C380000);
267 out32(GPIO1_TSRH, 0x00000000);
268 out32(GPIO1_ISR1L, 0x0FC30000);
269 out32(GPIO1_ISR1H, 0x00000000);
270 out32(GPIO1_ISR2L, 0x0C010000);
271 out32(GPIO1_ISR2H, 0x00000000);
272 out32(GPIO1_ISR3L, 0x01400000);
273 out32(GPIO1_ISR3H, 0x00000000);
275 configure_ppc440ep_pins();
282 char *s = getenv("serial#");
284 printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
294 /*************************************************************************
296 * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM)
298 * Fixed memory is composed of :
299 * MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
300 * 13 row add bits, 10 column add bits (but 12 row used only).
301 * ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
302 * 12 row add bits, 10 column add bits.
303 * Prepare a subset (only the used ones) of SPD data
305 * Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
306 * the corresponding bank is divided by 2 due to number of Row addresses
307 * 12 in the ECC module
309 * Assumes: 64 MB, ECC, non-registered
312 ************************************************************************/
313 static void init_spd_array(void)
315 cfg_simulate_spd_eeprom[8] = 0x04; /* 2.5 Volt */
316 cfg_simulate_spd_eeprom[2] = 0x07; /* DDR ram */
318 #ifdef CONFIG_DDR_ECC
319 cfg_simulate_spd_eeprom[11] = 0x02; /* ECC ON : 02 OFF : 00 */
320 cfg_simulate_spd_eeprom[31] = 0x08; /* bankSizeID: 32MB */
321 cfg_simulate_spd_eeprom[3] = 0x0C; /* num Row Addr: 12 */
323 cfg_simulate_spd_eeprom[11] = 0x00; /* ECC ON : 02 OFF : 00 */
324 cfg_simulate_spd_eeprom[31] = 0x10; /* bankSizeID: 64MB */
325 cfg_simulate_spd_eeprom[3] = 0x0D; /* num Row Addr: 13 */
328 cfg_simulate_spd_eeprom[4] = 0x09; /* numColAddr: 9 */
329 cfg_simulate_spd_eeprom[5] = 0x01; /* numBanks: 1 */
330 cfg_simulate_spd_eeprom[0] = 0x80; /* number of SPD bytes used: 128 */
331 cfg_simulate_spd_eeprom[1] = 0x08; /* total number bytes in SPD device = 256 */
332 cfg_simulate_spd_eeprom[21] = 0x00; /* not registered: 0 registered : 0x02*/
333 cfg_simulate_spd_eeprom[6] = 0x20; /* Module data width: 32 bits */
334 cfg_simulate_spd_eeprom[7] = 0x00; /* Module data width continued: +0 */
335 cfg_simulate_spd_eeprom[15] = 0x01; /* wcsbc = 1 */
336 cfg_simulate_spd_eeprom[27] = 0x50; /* tRpNs = 20 ns */
337 cfg_simulate_spd_eeprom[29] = 0x50; /* tRcdNs = 20 ns */
339 cfg_simulate_spd_eeprom[30] = 45; /* tRasNs */
341 cfg_simulate_spd_eeprom[18] = 0x0C; /* casBit (2,2.5) */
343 cfg_simulate_spd_eeprom[9] = 0x75; /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
344 cfg_simulate_spd_eeprom[23] = 0xA0; /* SDRAM Cycle Time (cas latency 2) = 10 ns */
345 cfg_simulate_spd_eeprom[25] = 0x00; /* SDRAM Cycle Time (cas latency 1.5) = N.A */
346 cfg_simulate_spd_eeprom[12] = 0x82; /* refresh Rate Type: Normal (15.625us) + Self refresh */
349 long int initdram (int board_type)
354 * First write simulated values in eeprom array for onboard bank 0
358 dram_size = spd_sdram();
363 #if defined(CFG_DRAM_TEST)
366 unsigned long *mem = (unsigned long *)0;
367 const unsigned long kend = (1024 / sizeof(unsigned long));
372 for (k = 0; k < CFG_KBYTES_SDRAM;
373 ++k, mem += (1024 / sizeof(unsigned long))) {
374 if ((k & 1023) == 0) {
375 printf("%3d MB\r", k / 1024);
378 memset(mem, 0xaaaaaaaa, 1024);
379 for (n = 0; n < kend; ++n) {
380 if (mem[n] != 0xaaaaaaaa) {
381 printf("SDRAM test fails at: %08x\n",
387 memset(mem, 0x55555555, 1024);
388 for (n = 0; n < kend; ++n) {
389 if (mem[n] != 0x55555555) {
390 printf("SDRAM test fails at: %08x\n",
396 printf("SDRAM test passes\n");
401 /*************************************************************************
404 * This routine is called just prior to registering the hose and gives
405 * the board the opportunity to check things. Returning a value of zero
406 * indicates that things are bad & PCI initialization should be aborted.
408 * Different boards may wish to customize the pci controller structure
409 * (add regions, override default access routines, etc) or perform
410 * certain pre-initialization actions.
412 ************************************************************************/
413 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
414 int pci_pre_init(struct pci_controller *hose)
418 /*-------------------------------------------------------------------------+
419 | Set priority for all PLB3 devices to 0.
420 | Set PLB3 arbiter to fair mode.
421 +-------------------------------------------------------------------------*/
422 mfsdr(sdr_amp1, addr);
423 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
424 addr = mfdcr(plb3_acr);
425 mtdcr(plb3_acr, addr | 0x80000000);
427 /*-------------------------------------------------------------------------+
428 | Set priority for all PLB4 devices to 0.
429 +-------------------------------------------------------------------------*/
430 mfsdr(sdr_amp0, addr);
431 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
432 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
433 mtdcr(plb4_acr, addr);
435 /*-------------------------------------------------------------------------+
436 | Set Nebula PLB4 arbiter to fair mode.
437 +-------------------------------------------------------------------------*/
439 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
440 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
441 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
442 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
443 mtdcr(plb0_acr, addr);
446 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
447 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
448 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
449 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
450 mtdcr(plb1_acr, addr);
454 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
456 /*************************************************************************
459 * The bootstrap configuration provides default settings for the pci
460 * inbound map (PIM). But the bootstrap config choices are limited and
461 * may not be sufficient for a given board.
463 ************************************************************************/
464 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
465 void pci_target_init(struct pci_controller *hose)
467 /*--------------------------------------------------------------------------+
468 * Set up Direct MMIO registers
469 *--------------------------------------------------------------------------*/
470 /*--------------------------------------------------------------------------+
471 | PowerPC440 EP PCI Master configuration.
472 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
473 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
474 | Use byte reversed out routines to handle endianess.
475 | Make this region non-prefetchable.
476 +--------------------------------------------------------------------------*/
477 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
478 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
479 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
480 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
481 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
483 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
484 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
485 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
486 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
487 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
489 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
490 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
491 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
492 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
494 /*--------------------------------------------------------------------------+
495 * Set up Configuration registers
496 *--------------------------------------------------------------------------*/
498 /* Program the board's subsystem id/vendor id */
499 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
500 CFG_PCI_SUBSYS_VENDORID);
501 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
503 /* Configure command register as bus master */
504 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
506 /* 240nS PCI clock */
507 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
509 /* No error reporting */
510 pci_write_config_word(0, PCI_ERREN, 0);
512 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
515 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
517 /*************************************************************************
520 ************************************************************************/
521 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
522 void pci_master_init(struct pci_controller *hose)
524 unsigned short temp_short;
526 /*--------------------------------------------------------------------------+
527 | Write the PowerPC440 EP PCI Configuration regs.
528 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
529 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
530 +--------------------------------------------------------------------------*/
531 pci_read_config_word(0, PCI_COMMAND, &temp_short);
532 pci_write_config_word(0, PCI_COMMAND,
533 temp_short | PCI_COMMAND_MASTER |
536 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
538 /*************************************************************************
541 * This routine is called to determine if a pci scan should be
542 * performed. With various hardware environments (especially cPCI and
543 * PPMC) it's insufficient to depend on the state of the arbiter enable
544 * bit in the strap register, or generic host/adapter assumptions.
546 * Rather than hard-code a bad assumption in the general 440 code, the
547 * 440 pci code requires the board to decide at runtime.
549 * Return 0 for adapter mode, non-zero for host (monarch) mode.
552 ************************************************************************/
553 #if defined(CONFIG_PCI)
554 int is_pci_host(struct pci_controller *hose)
556 /* Bamboo is always configured as host. */
559 #endif /* defined(CONFIG_PCI) */
561 /*----------------------------------------------------------------------------+
562 | is_powerpc440ep_pass1.
563 +----------------------------------------------------------------------------*/
564 int is_powerpc440ep_pass1(void)
570 if (pvr == PVR_POWERPC_440EP_PASS1)
572 else if (pvr == PVR_POWERPC_440EP_PASS2)
575 printf("brdutil error 3\n");
583 /*----------------------------------------------------------------------------+
585 +----------------------------------------------------------------------------*/
586 int is_nand_selected(void)
588 #ifdef CONFIG_BAMBOO_NAND
595 /*----------------------------------------------------------------------------+
596 | config_on_ebc_cs4_is_small_flash => from EPLD
597 +----------------------------------------------------------------------------*/
598 unsigned char config_on_ebc_cs4_is_small_flash(void)
600 /* Not implemented yet => returns constant value */
604 /*----------------------------------------------------------------------------+
605 | Ext_bus_cntlr_init.
606 | Initialize the external bus controller
607 +----------------------------------------------------------------------------*/
608 void ext_bus_cntlr_init(void)
610 unsigned long sdr0_pstrp0, sdr0_sdstp1;
611 unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
612 int computed_boot_device = BOOT_DEVICE_UNKNOWN;
613 unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
614 unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
615 unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
616 unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
617 unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
620 /*-------------------------------------------------------------------------+
622 | PART 1 : Initialize EBC Bank 5
623 | ==============================
624 | Bank5 is always associated to the NVRAM/EPLD.
625 | It has to be initialized prior to other banks settings computation since
626 | some board registers values may be needed
628 +-------------------------------------------------------------------------*/
630 mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
631 mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
633 /*-------------------------------------------------------------------------+
635 | PART 2 : Determine which boot device was selected
636 | =========================================
638 | Read Pin Strap Register in PPC440EP
639 | In case of boot from IIC, read Serial Device Strap Register1
641 | Result can either be :
642 | - Boot from EBC 8bits => SMALL FLASH
643 | - Boot from EBC 16bits => Large Flash or SRAM
644 | - Boot from NAND Flash
647 +-------------------------------------------------------------------------*/
648 /* Read Pin Strap Register in PPC440EP */
649 mfsdr(sdr_pstrp0, sdr0_pstrp0);
650 bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
652 /*-------------------------------------------------------------------------+
654 +-------------------------------------------------------------------------*/
655 if (is_powerpc440ep_pass1() == TRUE) {
656 switch(bootstrap_settings) {
657 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
658 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
659 /* Boot from Small Flash */
660 computed_boot_device = BOOT_FROM_SMALL_FLASH;
662 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
663 /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
665 computed_boot_device = BOOT_FROM_PCI;
668 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
669 /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
670 /* Boot from Nand Flash */
671 computed_boot_device = BOOT_FROM_NAND_FLASH0;
674 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
675 /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
676 /* Boot from Small Flash */
677 computed_boot_device = BOOT_FROM_SMALL_FLASH;
680 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
681 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
682 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
683 /* Read Serial Device Strap Register1 in PPC440EP */
684 mfsdr(sdr_sdstp1, sdr0_sdstp1);
685 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
686 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
688 switch(boot_selection) {
689 case SDR0_SDSTP1_BOOT_SEL_EBC:
690 switch(ebc_boot_size) {
691 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
692 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
694 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
695 computed_boot_device = BOOT_FROM_SMALL_FLASH;
700 case SDR0_SDSTP1_BOOT_SEL_PCI:
701 computed_boot_device = BOOT_FROM_PCI;
704 case SDR0_SDSTP1_BOOT_SEL_NDFC:
705 computed_boot_device = BOOT_FROM_NAND_FLASH0;
712 /*-------------------------------------------------------------------------+
714 +-------------------------------------------------------------------------*/
716 switch(bootstrap_settings) {
717 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
718 /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
719 /* Boot from Small Flash */
720 computed_boot_device = BOOT_FROM_SMALL_FLASH;
722 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
723 /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
725 computed_boot_device = BOOT_FROM_PCI;
728 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
729 /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
730 /* Boot from Nand Flash */
731 computed_boot_device = BOOT_FROM_NAND_FLASH0;
734 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
735 /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
736 /* Boot from Large Flash or SRAM */
737 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
740 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
741 /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
742 /* Boot from Large Flash or SRAM */
743 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
746 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
747 /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
749 computed_boot_device = BOOT_FROM_PCI;
752 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
753 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
754 /* Default Strap Settings 5-7 */
755 /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
756 /* Read Serial Device Strap Register1 in PPC440EP */
757 mfsdr(sdr_sdstp1, sdr0_sdstp1);
758 boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
759 ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
761 switch(boot_selection) {
762 case SDR0_SDSTP1_BOOT_SEL_EBC:
763 switch(ebc_boot_size) {
764 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
765 computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
767 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
768 computed_boot_device = BOOT_FROM_SMALL_FLASH;
773 case SDR0_SDSTP1_BOOT_SEL_PCI:
774 computed_boot_device = BOOT_FROM_PCI;
777 case SDR0_SDSTP1_BOOT_SEL_NDFC:
778 computed_boot_device = BOOT_FROM_NAND_FLASH0;
785 /*-------------------------------------------------------------------------+
787 | PART 3 : Compute EBC settings depending on selected boot device
788 | ====== ======================================================
790 | Resulting EBC init will be among following configurations :
792 | - Boot from EBC 8bits => boot from SMALL FLASH selected
793 | EBC-CS0 = Small Flash
794 | EBC-CS1,2,3 = NAND Flash or
795 | Exp.Slot depending on Soft Config
796 | EBC-CS4 = SRAM/Large Flash or
797 | Large Flash/SRAM depending on jumpers
798 | EBC-CS5 = NVRAM / EPLD
800 | - Boot from EBC 16bits => boot from Large Flash or SRAM selected
801 | EBC-CS0 = SRAM/Large Flash or
802 | Large Flash/SRAM depending on jumpers
803 | EBC-CS1,2,3 = NAND Flash or
804 | Exp.Slot depending on Software Configuration
805 | EBC-CS4 = Small Flash
806 | EBC-CS5 = NVRAM / EPLD
808 | - Boot from NAND Flash
809 | EBC-CS0 = NAND Flash0
810 | EBC-CS1,2,3 = NAND Flash1
811 | EBC-CS4 = SRAM/Large Flash or
812 | Large Flash/SRAM depending on jumpers
813 | EBC-CS5 = NVRAM / EPLD
817 | EBC-CS1,2,3 = NAND Flash or
818 | Exp.Slot depending on Software Configuration
819 | EBC-CS4 = SRAM/Large Flash or
820 | Large Flash/SRAM or
821 | Small Flash depending on jumpers
822 | EBC-CS5 = NVRAM / EPLD
824 +-------------------------------------------------------------------------*/
826 switch(computed_boot_device) {
827 /*------------------------------------------------------------------------- */
828 case BOOT_FROM_SMALL_FLASH:
829 /*------------------------------------------------------------------------- */
830 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
831 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
832 if ((is_nand_selected()) == TRUE) {
834 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
835 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
836 ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
837 ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
838 ebc0_cs3_bnap_value = 0;
839 ebc0_cs3_bncr_value = 0;
842 ebc0_cs1_bnap_value = 0;
843 ebc0_cs1_bncr_value = 0;
844 ebc0_cs2_bnap_value = 0;
845 ebc0_cs2_bncr_value = 0;
846 ebc0_cs3_bnap_value = 0;
847 ebc0_cs3_bncr_value = 0;
849 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
850 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
854 /*------------------------------------------------------------------------- */
855 case BOOT_FROM_LARGE_FLASH_OR_SRAM:
856 /*------------------------------------------------------------------------- */
857 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
858 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
859 if ((is_nand_selected()) == TRUE) {
861 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
862 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
863 ebc0_cs2_bnap_value = 0;
864 ebc0_cs2_bncr_value = 0;
865 ebc0_cs3_bnap_value = 0;
866 ebc0_cs3_bncr_value = 0;
869 ebc0_cs1_bnap_value = 0;
870 ebc0_cs1_bncr_value = 0;
871 ebc0_cs2_bnap_value = 0;
872 ebc0_cs2_bncr_value = 0;
873 ebc0_cs3_bnap_value = 0;
874 ebc0_cs3_bncr_value = 0;
876 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
877 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
881 /*------------------------------------------------------------------------- */
882 case BOOT_FROM_NAND_FLASH0:
883 /*------------------------------------------------------------------------- */
884 ebc0_cs0_bnap_value = 0;
885 ebc0_cs0_bncr_value = 0;
887 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
888 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
889 ebc0_cs2_bnap_value = 0;
890 ebc0_cs2_bncr_value = 0;
891 ebc0_cs3_bnap_value = 0;
892 ebc0_cs3_bncr_value = 0;
894 /* Large Flash or SRAM */
895 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
896 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
900 /*------------------------------------------------------------------------- */
902 /*------------------------------------------------------------------------- */
903 ebc0_cs0_bnap_value = 0;
904 ebc0_cs0_bncr_value = 0;
906 if ((is_nand_selected()) == TRUE) {
908 ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
909 ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
910 ebc0_cs2_bnap_value = 0;
911 ebc0_cs2_bncr_value = 0;
912 ebc0_cs3_bnap_value = 0;
913 ebc0_cs3_bncr_value = 0;
916 ebc0_cs1_bnap_value = 0;
917 ebc0_cs1_bncr_value = 0;
918 ebc0_cs2_bnap_value = 0;
919 ebc0_cs2_bncr_value = 0;
920 ebc0_cs3_bnap_value = 0;
921 ebc0_cs3_bncr_value = 0;
924 if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
926 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
927 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
929 /* Large Flash or SRAM */
930 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
931 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
936 /*------------------------------------------------------------------------- */
937 case BOOT_DEVICE_UNKNOWN:
938 /*------------------------------------------------------------------------- */
945 /*-------------------------------------------------------------------------+
946 | Initialize EBC CONFIG
947 +-------------------------------------------------------------------------*/
948 mtdcr(ebccfga, xbcfg);
949 mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN |
950 EBC0_CFG_PTD_ENABLED |
951 EBC0_CFG_RTC_2048PERCLK |
954 EBC0_CFG_CSTC_DRIVEN |
957 EBC0_CFG_PME_DISABLED |
958 EBC0_CFG_PMT_ENCODE(0) );
960 /*-------------------------------------------------------------------------+
961 | Initialize EBC Bank 0-4
962 +-------------------------------------------------------------------------*/
964 mtebc(pb0ap, ebc0_cs0_bnap_value);
965 mtebc(pb0cr, ebc0_cs0_bncr_value);
967 mtebc(pb1ap, ebc0_cs1_bnap_value);
968 mtebc(pb1cr, ebc0_cs1_bncr_value);
970 mtebc(pb2ap, ebc0_cs2_bnap_value);
971 mtebc(pb2cr, ebc0_cs2_bncr_value);
973 mtebc(pb3ap, ebc0_cs3_bnap_value);
974 mtebc(pb3cr, ebc0_cs3_bncr_value);
976 mtebc(pb4ap, ebc0_cs4_bnap_value);
977 mtebc(pb4cr, ebc0_cs4_bncr_value);
983 /*----------------------------------------------------------------------------+
984 | get_uart_configuration.
985 +----------------------------------------------------------------------------*/
986 uart_config_nb_t get_uart_configuration(void)
991 /*----------------------------------------------------------------------------+
992 | set_phy_configuration_through_fpga => to EPLD
993 +----------------------------------------------------------------------------*/
994 void set_phy_configuration_through_fpga(zmii_config_t config)
997 unsigned long fpga_selection_reg;
999 fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
1003 case ZMII_CONFIGURATION_IS_MII:
1004 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
1006 case ZMII_CONFIGURATION_IS_RMII:
1007 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
1009 case ZMII_CONFIGURATION_IS_SMII:
1010 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
1012 case ZMII_CONFIGURATION_UNKNOWN:
1016 out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
1020 /*----------------------------------------------------------------------------+
1021 | scp_selection_in_fpga.
1022 +----------------------------------------------------------------------------*/
1023 void scp_selection_in_fpga(void)
1025 unsigned long fpga_selection_2_reg;
1027 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1028 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
1029 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1032 /*----------------------------------------------------------------------------+
1033 | iic1_selection_in_fpga.
1034 +----------------------------------------------------------------------------*/
1035 void iic1_selection_in_fpga(void)
1037 unsigned long fpga_selection_2_reg;
1039 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1040 fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
1041 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1044 /*----------------------------------------------------------------------------+
1045 | dma_a_b_selection_in_fpga.
1046 +----------------------------------------------------------------------------*/
1047 void dma_a_b_selection_in_fpga(void)
1049 unsigned long fpga_selection_2_reg;
1051 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
1052 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1055 /*----------------------------------------------------------------------------+
1056 | dma_a_b_unselect_in_fpga.
1057 +----------------------------------------------------------------------------*/
1058 void dma_a_b_unselect_in_fpga(void)
1060 unsigned long fpga_selection_2_reg;
1062 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
1063 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1066 /*----------------------------------------------------------------------------+
1067 | dma_c_d_selection_in_fpga.
1068 +----------------------------------------------------------------------------*/
1069 void dma_c_d_selection_in_fpga(void)
1071 unsigned long fpga_selection_2_reg;
1073 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
1074 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1077 /*----------------------------------------------------------------------------+
1078 | dma_c_d_unselect_in_fpga.
1079 +----------------------------------------------------------------------------*/
1080 void dma_c_d_unselect_in_fpga(void)
1082 unsigned long fpga_selection_2_reg;
1084 fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
1085 out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1088 /*----------------------------------------------------------------------------+
1089 | usb2_device_selection_in_fpga.
1090 +----------------------------------------------------------------------------*/
1091 void usb2_device_selection_in_fpga(void)
1093 unsigned long fpga_selection_1_reg;
1095 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
1096 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1099 /*----------------------------------------------------------------------------+
1100 | usb2_device_reset_through_fpga.
1101 +----------------------------------------------------------------------------*/
1102 void usb2_device_reset_through_fpga(void)
1104 /* Perform soft Reset pulse */
1105 unsigned long fpga_reset_reg;
1108 fpga_reset_reg = in8(FPGA_RESET_REG);
1109 out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1110 for (i=0; i<500; i++)
1112 out8(FPGA_RESET_REG,fpga_reset_reg);
1115 /*----------------------------------------------------------------------------+
1116 | usb2_host_selection_in_fpga.
1117 +----------------------------------------------------------------------------*/
1118 void usb2_host_selection_in_fpga(void)
1120 unsigned long fpga_selection_1_reg;
1122 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1123 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1126 /*----------------------------------------------------------------------------+
1127 | ndfc_selection_in_fpga.
1128 +----------------------------------------------------------------------------*/
1129 void ndfc_selection_in_fpga(void)
1131 unsigned long fpga_selection_1_reg;
1133 fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1134 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
1135 fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
1136 out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1139 /*----------------------------------------------------------------------------+
1140 | uart_selection_in_fpga.
1141 +----------------------------------------------------------------------------*/
1142 void uart_selection_in_fpga(uart_config_nb_t uart_config)
1145 unsigned char fpga_selection_3_reg;
1147 /* Read FPGA Reagister */
1148 fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1150 switch (uart_config)
1153 /* ----------------------------------------------------------------------- */
1154 /* L1 configuration: UART0 = 8 pins */
1155 /* ----------------------------------------------------------------------- */
1156 /* Configure FPGA */
1157 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1158 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
1159 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1164 /* ----------------------------------------------------------------------- */
1165 /* L2 configuration: UART0 = 4 pins */
1166 /* UART1 = 4 pins */
1167 /* ----------------------------------------------------------------------- */
1168 /* Configure FPGA */
1169 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1170 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
1171 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1176 /* ----------------------------------------------------------------------- */
1177 /* L3 configuration: UART0 = 4 pins */
1178 /* UART1 = 2 pins */
1179 /* UART2 = 2 pins */
1180 /* ----------------------------------------------------------------------- */
1181 /* Configure FPGA */
1182 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1183 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
1184 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1188 /* Configure FPGA */
1189 fpga_selection_3_reg = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1190 fpga_selection_3_reg = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
1191 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1196 /* Unsupported UART configuration number */
1205 /*----------------------------------------------------------------------------+
1207 +----------------------------------------------------------------------------*/
1208 void init_default_gpio(void)
1213 for(i=0; i<GPIO_MAX; i++)
1215 gpio_tab[GPIO0][i].add = GPIO0_BASE;
1216 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1217 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1221 for(i=0; i<GPIO_MAX; i++)
1223 gpio_tab[GPIO1][i].add = GPIO1_BASE;
1224 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1225 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1228 /* EBC_CS_N(5) - GPIO0_10 */
1229 gpio_tab[GPIO0][10].in_out = GPIO_OUT;
1230 gpio_tab[GPIO0][10].alt_nb = GPIO_ALT1;
1232 /* EBC_CS_N(4) - GPIO0_9 */
1233 gpio_tab[GPIO0][9].in_out = GPIO_OUT;
1234 gpio_tab[GPIO0][9].alt_nb = GPIO_ALT1;
1237 /*----------------------------------------------------------------------------+
1239 +------------------------------------------------------------------------------
1241 | Set UART Configuration in PowerPC440EP
1243 | +---------------------------------------------------------------------+
1244 | | Configuartion | Connector | Nb of pins | Pins | Associated |
1245 | | Number | Port Name | available | naming | CORE |
1246 | +-----------------+---------------+------------+--------+-------------+
1247 | | L1 | Port_A | 8 | UART | UART core 0 |
1248 | +-----------------+---------------+------------+--------+-------------+
1249 | | L2 | Port_A | 4 | UART1 | UART core 0 |
1250 | | (L2D) | Port_B | 4 | UART2 | UART core 1 |
1251 | +-----------------+---------------+------------+--------+-------------+
1252 | | L3 | Port_A | 4 | UART1 | UART core 0 |
1253 | | (L3D) | Port_B | 2 | UART2 | UART core 1 |
1254 | | | Port_C | 2 | UART3 | UART core 2 |
1255 | +-----------------+---------------+------------+--------+-------------+
1256 | | | Port_A | 2 | UART1 | UART core 0 |
1257 | | L4 | Port_B | 2 | UART2 | UART core 1 |
1258 | | (L4D) | Port_C | 2 | UART3 | UART core 2 |
1259 | | | Port_D | 2 | UART4 | UART core 3 |
1260 | +-----------------+---------------+------------+--------+-------------+
1264 | +------------------------------------------------------------------------------+
1265 | | GPIO | Aternate 1 | I/O | Alternate 2 | I/O | Alternate 3 | I/O |
1266 | +---------+------------------+-----+-----------------+-----+-------------+-----+
1267 | | GPIO1_2 | UART0_DCD_N | I | UART1_DSR_CTS_N | I | UART2_SOUT | O |
1268 | | GPIO1_3 | UART0_8PIN_DSR_N | I | UART1_RTS_DTR_N | O | UART2_SIN | I |
1269 | | GPIO1_4 | UART0_8PIN_CTS_N | I | NA | NA | UART3_SIN | I |
1270 | | GPIO1_5 | UART0_RTS_N | O | NA | NA | UART3_SOUT | O |
1271 | | GPIO1_6 | UART0_DTR_N | O | UART1_SOUT | O | NA | NA |
1272 | | GPIO1_7 | UART0_RI_N | I | UART1_SIN | I | NA | NA |
1273 | +------------------------------------------------------------------------------+
1276 +----------------------------------------------------------------------------*/
1278 void update_uart_ios(uart_config_nb_t uart_config)
1280 switch (uart_config)
1283 /* ----------------------------------------------------------------------- */
1284 /* L1 configuration: UART0 = 8 pins */
1285 /* ----------------------------------------------------------------------- */
1286 /* Update GPIO Configuration Table */
1287 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1288 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1290 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1291 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1293 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1294 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1296 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1297 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1299 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1300 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1302 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1303 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1308 /* ----------------------------------------------------------------------- */
1309 /* L2 configuration: UART0 = 4 pins */
1310 /* UART1 = 4 pins */
1311 /* ----------------------------------------------------------------------- */
1312 /* Update GPIO Configuration Table */
1313 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1314 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1316 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1317 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1319 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1320 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1322 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1323 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1325 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1326 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1328 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1329 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1334 /* ----------------------------------------------------------------------- */
1335 /* L3 configuration: UART0 = 4 pins */
1336 /* UART1 = 2 pins */
1337 /* UART2 = 2 pins */
1338 /* ----------------------------------------------------------------------- */
1339 /* Update GPIO Configuration Table */
1340 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1341 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1343 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1344 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1346 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1347 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1349 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1350 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1352 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1353 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1355 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1356 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1361 /* ----------------------------------------------------------------------- */
1362 /* L4 configuration: UART0 = 2 pins */
1363 /* UART1 = 2 pins */
1364 /* UART2 = 2 pins */
1365 /* UART3 = 2 pins */
1366 /* ----------------------------------------------------------------------- */
1367 /* Update GPIO Configuration Table */
1368 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1369 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1371 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1372 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1374 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1375 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1377 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1378 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1380 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1381 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1383 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1384 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1389 /* Unsupported UART configuration number */
1390 printf("ERROR - Unsupported UART configuration number.\n\n");
1397 /* Set input Selection Register on Alt_Receive for UART Input Core */
1398 out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1399 out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1400 out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1403 /*----------------------------------------------------------------------------+
1404 | update_ndfc_ios(void).
1405 +----------------------------------------------------------------------------*/
1406 void update_ndfc_ios(void)
1408 /* Update GPIO Configuration Table */
1409 gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
1410 gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
1413 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
1414 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1416 gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
1417 gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1421 /*----------------------------------------------------------------------------+
1422 | update_zii_ios(void).
1423 +----------------------------------------------------------------------------*/
1424 void update_zii_ios(void)
1426 /* Update GPIO Configuration Table */
1427 gpio_tab[GPIO0][12].in_out = GPIO_IN; /* ZII_p0Rxd(0) */
1428 gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
1430 gpio_tab[GPIO0][13].in_out = GPIO_IN; /* ZII_p0Rxd(1) */
1431 gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
1433 gpio_tab[GPIO0][14].in_out = GPIO_IN; /* ZII_p0Rxd(2) */
1434 gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
1436 gpio_tab[GPIO0][15].in_out = GPIO_IN; /* ZII_p0Rxd(3) */
1437 gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
1439 gpio_tab[GPIO0][16].in_out = GPIO_OUT; /* ZII_p0Txd(0) */
1440 gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
1442 gpio_tab[GPIO0][17].in_out = GPIO_OUT; /* ZII_p0Txd(1) */
1443 gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
1445 gpio_tab[GPIO0][18].in_out = GPIO_OUT; /* ZII_p0Txd(2) */
1446 gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
1448 gpio_tab[GPIO0][19].in_out = GPIO_OUT; /* ZII_p0Txd(3) */
1449 gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
1451 gpio_tab[GPIO0][20].in_out = GPIO_IN; /* ZII_p0Rx_er */
1452 gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
1454 gpio_tab[GPIO0][21].in_out = GPIO_IN; /* ZII_p0Rx_dv */
1455 gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
1457 gpio_tab[GPIO0][22].in_out = GPIO_IN; /* ZII_p0Crs */
1458 gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
1460 gpio_tab[GPIO0][23].in_out = GPIO_OUT; /* ZII_p0Tx_er */
1461 gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
1463 gpio_tab[GPIO0][24].in_out = GPIO_OUT; /* ZII_p0Tx_en */
1464 gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
1466 gpio_tab[GPIO0][25].in_out = GPIO_IN; /* ZII_p0Col */
1467 gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
1471 /*----------------------------------------------------------------------------+
1472 | update_uic_0_3_irq_ios().
1473 +----------------------------------------------------------------------------*/
1474 void update_uic_0_3_irq_ios(void)
1476 gpio_tab[GPIO1][8].in_out = GPIO_IN; /* UIC_IRQ(0) */
1477 gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1479 gpio_tab[GPIO1][9].in_out = GPIO_IN; /* UIC_IRQ(1) */
1480 gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1482 gpio_tab[GPIO1][10].in_out = GPIO_IN; /* UIC_IRQ(2) */
1483 gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1485 gpio_tab[GPIO1][11].in_out = GPIO_IN; /* UIC_IRQ(3) */
1486 gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1489 /*----------------------------------------------------------------------------+
1490 | update_uic_4_9_irq_ios().
1491 +----------------------------------------------------------------------------*/
1492 void update_uic_4_9_irq_ios(void)
1494 gpio_tab[GPIO1][12].in_out = GPIO_IN; /* UIC_IRQ(4) */
1495 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1497 gpio_tab[GPIO1][13].in_out = GPIO_IN; /* UIC_IRQ(6) */
1498 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1500 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* UIC_IRQ(7) */
1501 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1503 gpio_tab[GPIO1][15].in_out = GPIO_IN; /* UIC_IRQ(8) */
1504 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1506 gpio_tab[GPIO1][16].in_out = GPIO_IN; /* UIC_IRQ(9) */
1507 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1510 /*----------------------------------------------------------------------------+
1511 | update_dma_a_b_ios().
1512 +----------------------------------------------------------------------------*/
1513 void update_dma_a_b_ios(void)
1515 gpio_tab[GPIO1][12].in_out = GPIO_OUT; /* DMA_ACK(1) */
1516 gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1518 gpio_tab[GPIO1][13].in_out = GPIO_BI; /* DMA_EOT/TC(1) */
1519 gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1521 gpio_tab[GPIO1][14].in_out = GPIO_IN; /* DMA_REQ(0) */
1522 gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1524 gpio_tab[GPIO1][15].in_out = GPIO_OUT; /* DMA_ACK(0) */
1525 gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1527 gpio_tab[GPIO1][16].in_out = GPIO_BI; /* DMA_EOT/TC(0) */
1528 gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1531 /*----------------------------------------------------------------------------+
1532 | update_dma_c_d_ios().
1533 +----------------------------------------------------------------------------*/
1534 void update_dma_c_d_ios(void)
1536 gpio_tab[GPIO0][0].in_out = GPIO_IN; /* DMA_REQ(2) */
1537 gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1539 gpio_tab[GPIO0][1].in_out = GPIO_OUT; /* DMA_ACK(2) */
1540 gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1542 gpio_tab[GPIO0][2].in_out = GPIO_BI; /* DMA_EOT/TC(2) */
1543 gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1545 gpio_tab[GPIO0][3].in_out = GPIO_IN; /* DMA_REQ(3) */
1546 gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1548 gpio_tab[GPIO0][4].in_out = GPIO_OUT; /* DMA_ACK(3) */
1549 gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1551 gpio_tab[GPIO0][5].in_out = GPIO_BI; /* DMA_EOT/TC(3) */
1552 gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1556 /*----------------------------------------------------------------------------+
1557 | update_ebc_master_ios().
1558 +----------------------------------------------------------------------------*/
1559 void update_ebc_master_ios(void)
1561 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* EXT_EBC_REQ */
1562 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1564 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1565 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1567 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* EBC_EXT_ACK */
1568 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1570 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* EBC_EXR_BUSREQ */
1571 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1574 /*----------------------------------------------------------------------------+
1575 | update_usb2_device_ios().
1576 +----------------------------------------------------------------------------*/
1577 void update_usb2_device_ios(void)
1579 gpio_tab[GPIO0][26].in_out = GPIO_IN; /* USB2D_RXVALID */
1580 gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1582 gpio_tab[GPIO0][27].in_out = GPIO_IN; /* USB2D_RXERROR */
1583 gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1585 gpio_tab[GPIO0][28].in_out = GPIO_OUT; /* USB2D_TXVALID */
1586 gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1588 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* USB2D_PAD_SUSPNDM */
1589 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1591 gpio_tab[GPIO0][30].in_out = GPIO_OUT; /* USB2D_XCVRSELECT */
1592 gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1594 gpio_tab[GPIO0][31].in_out = GPIO_OUT; /* USB2D_TERMSELECT */
1595 gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1597 gpio_tab[GPIO1][0].in_out = GPIO_OUT; /* USB2D_OPMODE0 */
1598 gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1600 gpio_tab[GPIO1][1].in_out = GPIO_OUT; /* USB2D_OPMODE1 */
1601 gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1605 /*----------------------------------------------------------------------------+
1606 | update_pci_patch_ios().
1607 +----------------------------------------------------------------------------*/
1608 void update_pci_patch_ios(void)
1610 gpio_tab[GPIO0][29].in_out = GPIO_OUT; /* EBC_EXT_HDLA */
1611 gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1614 /*----------------------------------------------------------------------------+
1615 | set_chip_gpio_configuration(unsigned char gpio_core)
1616 | Put the core impacted by clock modification and sharing in reset.
1617 | Config the select registers to resolve the sharing depending of the config.
1618 | Configure the GPIO registers.
1620 +----------------------------------------------------------------------------*/
1621 void set_chip_gpio_configuration(unsigned char gpio_core)
1623 unsigned char i=0, j=0, reg_offset = 0;
1624 unsigned long gpio_reg, gpio_core_add;
1626 /* GPIO config of the GPIOs 0 to 31 */
1627 for (i=0; i<GPIO_MAX; i++, j++)
1629 if (i == GPIO_MAX/2)
1635 gpio_core_add = gpio_tab[gpio_core][i].add;
1637 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1638 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1640 switch (gpio_tab[gpio_core][i].alt_nb)
1646 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1647 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1648 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1652 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1653 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1654 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1658 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1659 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1660 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1664 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1665 (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1668 switch (gpio_tab[gpio_core][i].alt_nb)
1673 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1674 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1675 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1676 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1677 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1678 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1681 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1682 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1683 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1684 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1685 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1686 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1689 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1690 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1691 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1692 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1693 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1694 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1701 /*----------------------------------------------------------------------------+
1702 | force_bup_core_selection.
1703 +----------------------------------------------------------------------------*/
1704 void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1706 /* Pointer invalid */
1707 if (core_select_P == NULL)
1709 printf("Configuration invalid pointer 1\n");
1715 *(core_select_P+UART_CORE0) = CORE_SELECTED;
1716 *(core_select_P+UART_CORE1) = CORE_SELECTED;
1717 *(core_select_P+UART_CORE2) = CORE_SELECTED;
1718 *(core_select_P+UART_CORE3) = CORE_SELECTED;
1720 /* RMII Selection */
1721 *(core_select_P+RMII_SEL) = CORE_SELECTED;
1723 /* External Interrupt 0-9 selection */
1724 *(core_select_P+UIC_0_3) = CORE_SELECTED;
1725 *(core_select_P+UIC_4_9) = CORE_SELECTED;
1727 *(core_select_P+SCP_CORE) = CORE_SELECTED;
1728 *(core_select_P+DMA_CHANNEL_CD) = CORE_SELECTED;
1729 *(core_select_P+PACKET_REJ_FUNC_AVAIL) = CORE_SELECTED;
1730 *(core_select_P+USB1_DEVICE) = CORE_SELECTED;
1732 if (is_nand_selected()) {
1733 *(core_select_P+NAND_FLASH) = CORE_SELECTED;
1736 *config_val_P = CONFIG_IS_VALID;
1740 /*----------------------------------------------------------------------------+
1741 | configure_ppc440ep_pins.
1742 +----------------------------------------------------------------------------*/
1743 void configure_ppc440ep_pins(void)
1745 uart_config_nb_t uart_configuration;
1746 config_validity_t config_val = CONFIG_IS_INVALID;
1748 /* Create Core Selection Table */
1749 core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1751 CORE_NOT_SELECTED, /* IIC_CORE, */
1752 CORE_NOT_SELECTED, /* SPC_CORE, */
1753 CORE_NOT_SELECTED, /* DMA_CHANNEL_AB, */
1754 CORE_NOT_SELECTED, /* UIC_4_9, */
1755 CORE_NOT_SELECTED, /* USB2_HOST, */
1756 CORE_NOT_SELECTED, /* DMA_CHANNEL_CD, */
1757 CORE_NOT_SELECTED, /* USB2_DEVICE, */
1758 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_AVAIL, */
1759 CORE_NOT_SELECTED, /* USB1_DEVICE, */
1760 CORE_NOT_SELECTED, /* EBC_MASTER, */
1761 CORE_NOT_SELECTED, /* NAND_FLASH, */
1762 CORE_NOT_SELECTED, /* UART_CORE0, */
1763 CORE_NOT_SELECTED, /* UART_CORE1, */
1764 CORE_NOT_SELECTED, /* UART_CORE2, */
1765 CORE_NOT_SELECTED, /* UART_CORE3, */
1766 CORE_NOT_SELECTED, /* MII_SEL, */
1767 CORE_NOT_SELECTED, /* RMII_SEL, */
1768 CORE_NOT_SELECTED, /* SMII_SEL, */
1769 CORE_NOT_SELECTED, /* PACKET_REJ_FUNC_EN */
1770 CORE_NOT_SELECTED, /* UIC_0_3 */
1771 CORE_NOT_SELECTED, /* USB1_HOST */
1772 CORE_NOT_SELECTED /* PCI_PATCH */
1776 /* Table Default Initialisation + FPGA Access */
1777 init_default_gpio();
1778 set_chip_gpio_configuration(GPIO0);
1779 set_chip_gpio_configuration(GPIO1);
1782 force_bup_core_selection(ppc440ep_core_selection, &config_val);
1783 #if 0 /* test-only */
1784 /* If we are running PIBS 1, force known configuration */
1785 update_core_selection_table(ppc440ep_core_selection, &config_val);
1788 /*----------------------------------------------------------------------------+
1789 | SDR + ios table update + fpga initialization
1790 +----------------------------------------------------------------------------*/
1791 unsigned long sdr0_pfc1 = 0;
1792 unsigned long sdr0_usb0 = 0;
1793 unsigned long sdr0_mfr = 0;
1795 /* PCI Always selected */
1798 if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1800 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1801 iic1_selection_in_fpga();
1805 if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1807 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1808 scp_selection_in_fpga();
1811 /* UIC 0:3 Selection */
1812 if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1814 update_uic_0_3_irq_ios();
1815 dma_a_b_unselect_in_fpga();
1818 /* UIC 4:9 Selection */
1819 if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1821 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
1822 update_uic_4_9_irq_ios();
1825 /* DMA AB Selection */
1826 if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1828 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
1829 update_dma_a_b_ios();
1830 dma_a_b_selection_in_fpga();
1833 /* DMA CD Selection */
1834 if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1836 update_dma_c_d_ios();
1837 dma_c_d_selection_in_fpga();
1840 /* EBC Master Selection */
1841 if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1843 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1844 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1845 update_ebc_master_ios();
1848 /* PCI Patch Enable */
1849 if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1851 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1852 update_pci_patch_ios();
1855 /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1856 if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1858 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1859 printf("Invalid configuration => USB2 Host selected\n");
1862 /*usb2_host_selection_in_fpga(); */
1865 /* USB2.0 Device Selection */
1866 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1868 update_usb2_device_ios();
1869 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
1870 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
1872 mfsdr(sdr_usb0, sdr0_usb0);
1873 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1874 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
1875 mtsdr(sdr_usb0, sdr0_usb0);
1877 usb2_device_selection_in_fpga();
1880 /* USB1.1 Device Selection */
1881 if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
1883 mfsdr(sdr_usb0, sdr0_usb0);
1884 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1885 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
1886 mtsdr(sdr_usb0, sdr0_usb0);
1889 /* USB1.1 Host Selection */
1890 if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
1892 mfsdr(sdr_usb0, sdr0_usb0);
1893 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
1894 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
1895 mtsdr(sdr_usb0, sdr0_usb0);
1898 /* NAND Flash Selection */
1899 if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
1903 mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
1904 SDR0_CUST0_NDFC_ENABLE |
1905 SDR0_CUST0_NDFC_BW_8_BIT |
1906 SDR0_CUST0_NDFC_ARE_MASK |
1907 SDR0_CUST0_CHIPSELGAT_EN1 |
1908 SDR0_CUST0_CHIPSELGAT_EN2);
1910 ndfc_selection_in_fpga();
1914 /* Set Mux on EMAC */
1915 mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
1919 if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
1922 mfsdr(sdr_mfr, sdr0_mfr);
1923 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
1924 mtsdr(sdr_mfr, sdr0_mfr);
1926 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
1929 /* RMII Selection */
1930 if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
1933 mfsdr(sdr_mfr, sdr0_mfr);
1934 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
1935 mtsdr(sdr_mfr, sdr0_mfr);
1937 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
1940 /* SMII Selection */
1941 if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
1944 mfsdr(sdr_mfr, sdr0_mfr);
1945 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
1946 mtsdr(sdr_mfr, sdr0_mfr);
1948 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
1951 /* UART Selection */
1952 uart_configuration = get_uart_configuration();
1953 switch (uart_configuration)
1955 case L1: /* L1 Selection */
1956 /* UART0 8 pins Only */
1957 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
1958 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS; /* Chip Pb */
1959 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
1961 case L2: /* L2 Selection */
1962 /* UART0 and UART1 4 pins */
1963 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1964 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1965 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1967 case L3: /* L3 Selection */
1968 /* UART0 4 pins, UART1 and UART2 2 pins */
1969 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1970 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1971 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1973 case L4: /* L4 Selection */
1974 /* UART0, UART1, UART2 and UART3 2 pins */
1975 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
1976 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1977 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1980 update_uart_ios(uart_configuration);
1982 /* UART Selection in all cases */
1983 uart_selection_in_fpga(uart_configuration);
1985 /* Packet Reject Function Available */
1986 if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
1988 /* Set UPR Bit in SDR0_PFC1 Register */
1989 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
1992 /* Packet Reject Function Enable */
1993 if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
1995 mfsdr(sdr_mfr, sdr0_mfr);
1996 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
1997 mtsdr(sdr_mfr, sdr0_mfr);
2000 /* Perform effective access to hardware */
2001 mtsdr(sdr_pfc1, sdr0_pfc1);
2002 set_chip_gpio_configuration(GPIO0);
2003 set_chip_gpio_configuration(GPIO1);
2005 /* USB2.0 Device Reset must be done after GPIO setting */
2006 if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
2007 usb2_device_reset_through_fpga();