3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/processor.h>
10 #include <asm/ppc405.h>
12 /* test-only: move into cpu directory!!! */
14 #if defined(PLLMR0_200_133_66)
15 void board_pll_init_f(void)
18 * set PLL clocks based on input sysclk is 33M
20 * ----------------------------------
21 * | CLK | FREQ (MHz) | DIV RATIO |
22 * ----------------------------------
23 * | CPU | 200.0 | 4 (0x02)|
24 * | PLB | 133.3 | 6 (0x06)|
25 * | OPB | 66.6 | 12 (0x0C)|
26 * | EBC | 66.6 | 12 (0x0C)|
27 * | SPI | 66.6 | 12 (0x0C)|
28 * | UART0 | 10.0 | 40 (0x28)|
29 * | UART1 | 10.0 | 40 (0x28)|
30 * | DAC | 2.0 | 200 (0xC8)|
31 * | ADC | 2.0 | 200 (0xC8)|
32 * | PWM | 100.0 | 4 (0x04)|
33 * | EMAC | 25.0 | 16 (0x10)|
34 * -----------------------------------
38 mtcpr(CPR0_PLLC, 0x0000033c);
39 mtcpr(CPR0_PLLD, 0x0c010200);
40 mtcpr(CPR0_PRIMAD, 0x04060c0c);
41 mtcpr(CPR0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
42 mtcpr(CPR0_CLKUPD, 0x40000000);
45 #elif defined(PLLMR0_266_160_80)
47 void board_pll_init_f(void)
50 * set PLL clocks based on input sysclk is 33M
52 * ----------------------------------
53 * | CLK | FREQ (MHz) | DIV RATIO |
54 * ----------------------------------
55 * | CPU | 266.64 | 3 |
56 * | PLB | 159.98 | 5 (0x05)|
57 * | OPB | 79.99 | 10 (0x0A)|
58 * | EBC | 79.99 | 10 (0x0A)|
59 * | SPI | 79.99 | 10 (0x0A)|
60 * | UART0 | 28.57 | 7 (0x07)|
61 * | UART1 | 28.57 | 7 (0x07)|
62 * | DAC | 28.57 | 7 (0xA7)|
63 * | ADC | 4 | 50 (0x32)|
64 * | PWM | 28.57 | 7 (0x07)|
65 * | EMAC | 4 | 50 (0x32)|
66 * -----------------------------------
70 mtcpr(CPR0_PLLC, 0x20000238);
71 mtcpr(CPR0_PLLD, 0x03010400);
72 mtcpr(CPR0_PRIMAD, 0x03050a0a);
73 mtcpr(CPR0_PERC0, 0x00000000);
74 mtcpr(CPR0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
75 mtcpr(CPR0_PERD1, 0x07323200);
76 mtcpr(CPR0_CLKUP, 0x40000000);
79 #elif defined(PLLMR0_333_166_83)
81 void board_pll_init_f(void)
84 * set PLL clocks based on input sysclk is 33M
86 * ----------------------------------
87 * | CLK | FREQ (MHz) | DIV RATIO |
88 * ----------------------------------
89 * | CPU | 333.33 | 2 |
90 * | PLB | 166.66 | 4 (0x04)|
91 * | OPB | 83.33 | 8 (0x08)|
92 * | EBC | 83.33 | 8 (0x08)|
93 * | SPI | 83.33 | 8 (0x08)|
94 * | UART0 | 16.66 | 5 (0x05)|
95 * | UART1 | 16.66 | 5 (0x05)|
96 * | DAC | ???? | 166 (0xA6)|
97 * | ADC | ???? | 166 (0xA6)|
98 * | PWM | 41.66 | 3 (0x03)|
99 * | EMAC | ???? | 3 (0x03)|
100 * -----------------------------------
104 mtcpr(CPR0_PLLC, 0x0000033C);
105 mtcpr(CPR0_PLLD, 0x0a010000);
106 mtcpr(CPR0_PRIMAD, 0x02040808);
107 mtcpr(CPR0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
108 mtcpr(CPR0_PERD1, 0xA6A60300);
109 mtcpr(CPR0_CLKUP, 0x40000000);
112 #elif defined(PLLMR0_100_100_12)
114 void board_pll_init_f(void)
117 * set PLL clocks based on input sysclk is 33M
119 * ----------------------
120 * | CLK | FREQ (MHz) |
121 * ----------------------
126 * ----------------------
130 mtcpr(CPR0_PLLC, 0x000003BC);
131 mtcpr(CPR0_PLLD, 0x06060600);
132 mtcpr(CPR0_PRIMAD, 0x02020004);
133 mtcpr(CPR0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
134 mtcpr(CPR0_PERD1, 0xC8C81600);
135 mtcpr(CPR0_CLKUP, 0x40000000);
137 #endif /* CPU_<speed>_405EZ */