3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* define DEBUG for debugging output (obviously ;-)) */
30 #include <asm/processor.h>
35 * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
42 static void cram_bcr_write(u32 wr_val)
46 /* set CRAM_CRE to 1 */
47 gpio_write_bit(CFG_GPIO_CRAM_CRE, 1);
49 /* Write BCR to CRAM on CS1 */
50 out32(wr_val + 0x00200000, 0);
51 debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
53 /* Write BCR to CRAM on CS2 */
54 out32(wr_val + 0x02200000, 0);
55 debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
60 /* set CRAM_CRE back to 0 (normal operation) */
61 gpio_write_bit(CFG_GPIO_CRAM_CRE, 0);
66 long int initdram(int board_type)
70 /* 1. EBC need to program READY, CLK, ADV for ASync mode */
71 gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
72 gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
73 gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
74 gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
76 /* 2. EBC in Async mode */
77 mtebc(pb1ap, 0x078F1EC0);
78 mtebc(pb2ap, 0x078F1EC0);
79 mtebc(pb1cr, 0x000BC000);
80 mtebc(pb2cr, 0x020BC000);
82 /* 3. Set CRAM in Sync mode */
83 cram_bcr_write(0x7012); /* CRAM burst setting */
85 /* 4. EBC in Sync mode */
86 mtebc(pb1ap, 0x9C0201C0);
87 mtebc(pb2ap, 0x9C0201C0);
89 /* Set GPIO pins back to alternate function */
90 gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
91 gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
93 /* Config EBC to use RDY */
94 mfsdr(sdrultra0, val);
95 mtsdr(sdrultra0, val | 0x04000000);
97 return (CFG_MBYTES_RAM << 20);