3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
27 #define CRAM_BANK0_BASE 0x0
28 #define CRAM_DIDR 0x00100000
29 #define MICRON_MT45W8MW16BGX_CRAM_ID 0x1b431b43
30 #define MICRON_MT45W8MW16BGX_CRAM_ID2 0x13431343
31 #define MICRON_DIDR_VENDOR_ID 0x00030003 /* 00011b */
32 #define CRAM_DIDR_VENDOR_ID_MASK 0x001f001f /* DIDR[4:0] */
33 #define CRAM_DEVID_NOT_SUPPORTED 0x00000000
35 #define PSRAM_PASS 0x50415353 /* "PASS" */
36 #define PSRAM_FAIL 0x4641494C /* "FAIL" */
38 static u32 is_cram_inited(void);
39 static u32 is_cram(void);
40 static long int cram_init(u32);
41 static void cram_bcr_write(u32);
42 void udelay (unsigned long);
46 volatile unsigned long spr_reg;
49 * If CRAM not initialized or CRAM looks initialized because this
50 * is after a warm reboot then set SPRG7 to indicate CRAM needs
51 * initialization. Note that CRAM is initialized by the SPI and
54 spr_reg = (volatile unsigned long) mfspr(SPRG6);
55 if ((is_cram_inited() != 1) || (spr_reg != LOAK_SPL)) {
56 mtspr(SPRG7, LOAK_NONE); /* "NONE" */
60 * When running the NAND SPL, the normal EBC configuration is not
61 * done, so We need to enable EPLD access on EBC_CS_2 and the memory
65 /* Enable CPLD - Needed for PSRAM Access */
68 /* Init SDRAM by setting EBC Bank 3 for PSRAM */
69 mtebc(pb1ap, CFG_EBC_PB1AP);
70 mtebc(pb1cr, CFG_EBC_PB1CR);
72 mtebc(pb2ap, CFG_EBC_PB2AP);
73 mtebc(pb2cr, CFG_EBC_PB2CR);
75 /* pre-boot loader code: we are in OCM */
76 mtspr(SPRG6, LOAK_SPL); /* "SPL " */
77 mtspr(SPRG7, LOAK_OCM); /* "OCM " */
82 static void cram_bcr_write(u32 wr_val)
86 volatile u32 gpio_reg;
88 /* # Program CRAM write */
92 * set wr_val = wr_val << 2
94 gpio_reg = in32(GPIO1_OR);
95 out32(GPIO1_OR, gpio_reg | 0x00000400);
97 /* wr_val = 0x1c048; */
100 * # stop PLL clock before programming CRAM
101 * set EPLD0_MUX_CTL.OESPR3 = 1
108 * #shift 2 bit left before write
109 * set val = wr_val + 0x00200000
111 * read 0x00200000 val
114 tmp_reg = in32(0x00200000);
115 val = wr_val + 0x00200000;
116 /* val = 0x0021c048; */
119 val = in32(0x00200000);
121 debug("CRAM VAL: %x for CS1 ", val);
126 * #shift 2 bit left before write
127 * set val = wr_val + 0x02200000
129 * read 0x02200000 val
132 tmp_reg = in32(0x02200000);
133 val = wr_val + 0x02200000;
134 /* val = 0x0221c048; */
137 val = in32(0x02200000);
139 debug("CRAM VAL: %x for CS2 ", val);
142 * # Start PLL clock before programming CRAM
143 * set EPLD0_MUX_CTL.OESPR3 = 0
149 gpio_reg = in32(GPIO1_OR);
150 out32(GPIO1_OR, gpio_reg | 0x00000400);
153 * # read CRAM config BCR ( bit19:18 = 10b )
155 * # 1001_1001_0001_1111 ( 991f ) =>
156 * #10_0110_0100_0111_1100 => 2647c => 0022647c
157 * #0011_0010_0011_1110 (323e)
162 * set EPLD0_MUX_CTL.CRAMCR = 0x0
164 gpio_reg = in32(GPIO1_OR);
165 out32(GPIO1_OR, gpio_reg & 0xFFFFFBFF);
169 static u32 is_cram_inited()
171 volatile unsigned long spr_reg;
174 * If CRAM is initialized already, then don't reinitialize it again.
175 * In the case of NAND boot and SPI boot, CRAM will already be
176 * initialized by the pre-loader
178 spr_reg = (volatile unsigned long) mfspr(SPRG7);
179 if (spr_reg == LOAK_CRAM) {
187 * return 0 if not CRAM
188 * return 1 if CRAM and it's already inited by preloader
189 * else return cram_id (CRAM Device Identification Register)
191 static u32 is_cram(void)
193 u32 gpio_TCR, gpio_OSRL, gpio_OR, gpio_ISR1L;
194 volatile u32 gpio_reg;
195 volatile u32 cram_id = 0;
197 if (is_cram_inited() == 1) {
198 /* this is CRAM and it is already inited (by preloader) */
203 * set GPIO0_TCR.G8 = 1
204 * set GPIO0_OSRL.G8 = 0
205 * set GPIO0_OR.G8 = 0
207 gpio_reg = in32(GPIO0_TCR);
209 out32(GPIO0_TCR, gpio_reg | 0x00800000);
210 gpio_reg = in32(GPIO0_OSRL);
211 gpio_OSRL = gpio_reg;
212 out32(GPIO0_OSRL, gpio_reg & 0xffffbfff);
213 gpio_reg = in32(GPIO0_OR);
215 out32(GPIO0_OR, gpio_reg & 0xff7fffff);
218 * # CRAM Addreaa Valid
219 * set GPIO0_TCR.G10 = 1
220 * set GPIO0_OSRL.G10 = 0
221 * set GPIO0_OR.G10 = 0
223 gpio_reg = in32(GPIO0_TCR);
224 out32(GPIO0_TCR, gpio_reg | 0x00200000);
225 gpio_reg = in32(GPIO0_OSRL);
226 out32(GPIO0_OSRL, gpio_reg & 0xfffffbff);
227 gpio_reg = in32(GPIO0_OR);
228 out32(GPIO0_OR, gpio_reg & 0xffdfffff);
231 * # config input (EBC_WAIT)
232 * set GPIO0_ISR1L.G9 = 1
233 * set GPIO0_TCR.G9 = 0
235 gpio_reg = in32(GPIO0_ISR1L);
236 gpio_ISR1L = gpio_reg;
237 out32(GPIO0_ISR1L, gpio_reg | 0x00001000);
238 gpio_reg = in32(GPIO0_TCR);
239 out32(GPIO0_TCR, gpio_reg & 0xffbfffff);
242 * Enable CRE to read Registers
243 * set GPIO0_TCR.21 = 1
244 * set GPIO1_OR.21 = 1
246 gpio_reg = in32(GPIO1_TCR);
247 out32(GPIO1_TCR, gpio_reg | 0x00000400);
249 gpio_reg = in32(GPIO1_OR);
250 out32(GPIO1_OR, gpio_reg | 0x00000400);
252 /* Read Version ID */
253 cram_id = (volatile u32) in32(CRAM_BANK0_BASE+CRAM_DIDR);
256 asm volatile(" sync");
257 asm volatile(" eieio");
259 debug("Cram ID: %X ", cram_id);
262 case MICRON_MT45W8MW16BGX_CRAM_ID:
263 case MICRON_MT45W8MW16BGX_CRAM_ID2:
264 /* supported CRAM vendor/part */
266 case CRAM_DEVID_NOT_SUPPORTED:
268 /* check for DIDR Vendor ID of Micron */
269 if ((cram_id & CRAM_DIDR_VENDOR_ID_MASK) ==
270 MICRON_DIDR_VENDOR_ID)
272 /* supported CRAM vendor */
275 /* this is not CRAM or not supported CRAM vendor/part */
278 * reset the GPIO registers to the values that were
279 * there before this routine
281 out32(GPIO0_TCR, gpio_TCR);
282 out32(GPIO0_OSRL, gpio_OSRL);
283 out32(GPIO0_OR, gpio_OR);
284 out32(GPIO0_ISR1L, gpio_ISR1L);
292 static long int cram_init(u32 already_inited)
294 volatile u32 tmp_reg;
297 if (already_inited == 0) return 0;
300 * If CRAM is initialized already, then don't reinitialize it again.
301 * In the case of NAND boot and SPI boot, CRAM will already be
302 * initialized by the pre-loader
304 if (already_inited != 1) {
307 * # - CRAMCRE @reg16 = 1; for CRAM to use
308 * # - CRAMCRE @reg16 = 0; for CRAM to program
310 * # enable CRAM SEL, move from setEPLD.cmd
311 * set EPLD0_MUX_CTL.OECRAM = 0
312 * set EPLD0_MUX_CTL.CRAMCR = 1
313 * set EPLD0_ETHRSTBOOT.SLCRAM = 0
318 * #1. EBC need to program READY, CLK, ADV for ASync mode
324 * set GPIO0_TCR.G8 = 1
325 * set GPIO0_OSRL.G8 = 0
326 * set GPIO0_OR.G8 = 0
328 tmp_reg = in32(GPIO0_TCR);
329 out32(GPIO0_TCR, tmp_reg | 0x00800000);
330 tmp_reg = in32(GPIO0_OSRL);
331 out32(GPIO0_OSRL, tmp_reg & 0xffffbfff);
332 tmp_reg = in32(GPIO0_OR);
333 out32(GPIO0_OR, tmp_reg & 0xff7fffff);
336 * # CRAM Addreaa Valid
337 * set GPIO0_TCR.G10 = 1
338 * set GPIO0_OSRL.G10 = 0
339 * set GPIO0_OR.G10 = 0
341 tmp_reg = in32(GPIO0_TCR);
342 out32(GPIO0_TCR, tmp_reg | 0x00200000);
343 tmp_reg = in32(GPIO0_OSRL);
344 out32(GPIO0_OSRL, tmp_reg & 0xfffffbff);
345 tmp_reg = in32(GPIO0_OR);
346 out32(GPIO0_OR, tmp_reg & 0xffdfffff);
349 * # config input (EBC_WAIT)
350 * set GPIO0_ISR1L.G9 = 1
351 * set GPIO0_TCR.G9 = 0
353 tmp_reg = in32(GPIO0_ISR1L);
354 out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
355 tmp_reg = in32(GPIO0_TCR);
356 out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
359 * # config CS4 from GPIO
360 * set GPIO0_TCR.G0 = 1
361 * set GPIO0_OSRL.G0 = 1
363 tmp_reg = in32(GPIO0_TCR);
364 out32(GPIO0_TCR, tmp_reg | 0x80000000);
365 tmp_reg = in32(GPIO0_OSRL);
366 out32(GPIO0_OSRL, tmp_reg | 0x40000000);
369 * #2. EBC in Async mode
370 * # set EBC0_PB1AP = 0x078f0ec0
371 * set EBC0_PB1AP = 0x078f1ec0
372 * set EBC0_PB2AP = 0x078f1ec0
374 mtebc(pb1ap, 0x078F1EC0);
375 mtebc(pb2ap, 0x078F1EC0);
378 * #set EBC0_PB1CR = 0x000bc000
379 * #enable CS2 for CRAM
380 * set EBC0_PB2CR = 0x020bc000
382 mtebc(pb1cr, 0x000BC000);
383 mtebc(pb2cr, 0x020BC000);
386 * #3. set CRAM in Sync mode
387 * #exec cm_bcr_write.cmd { 0x701f }
388 * #3. set CRAM in Sync mode (full drv strength)
389 * exec cm_bcr_write.cmd { 0x701F }
391 cram_wr_val = 0x7012; /* CRAM burst setting */
392 cram_bcr_write(cram_wr_val);
395 * #4. EBC in Sync mode
396 * #set EBC0_PB1AP = 0x9f800fc0
397 * #set EBC0_PB1AP = 0x900001c0
398 * set EBC0_PB2AP = 0x9C0201c0
399 * set EBC0_PB2AP = 0x9C0201c0
401 mtebc(pb1ap, 0x9C0201C0);
402 mtebc(pb2ap, 0x9C0201C0);
405 * #5. EBC need to program READY, CLK, ADV for Sync mode
407 * set GPIO0_TCR.G8 = 1
408 * set GPIO0_OSRL.G8 = 1
409 * set GPIO0_TCR.G10 = 1
410 * set GPIO0_OSRL.G10 = 1
412 tmp_reg = in32(GPIO0_TCR);
413 out32(GPIO0_TCR, tmp_reg | 0x00800000);
414 tmp_reg = in32(GPIO0_OSRL);
415 out32(GPIO0_OSRL, tmp_reg | 0x00004000);
416 tmp_reg = in32(GPIO0_TCR);
417 out32(GPIO0_TCR, tmp_reg | 0x00200000);
418 tmp_reg = in32(GPIO0_OSRL);
419 out32(GPIO0_OSRL, tmp_reg | 0x00000400);
423 * set GPIO0_ISR1L.G9 = 1
424 * set GPIO0_TCR.G9 = 0
426 tmp_reg = in32(GPIO0_ISR1L);
427 out32(GPIO0_ISR1L, tmp_reg | 0x00001000);
428 tmp_reg = in32(GPIO0_TCR);
429 out32(GPIO0_TCR, tmp_reg & 0xffbfffff);
432 * # config EBC to use RDY
433 * set SDR0_ULTRA0.EBCREN = 1
435 mfsdr(sdrultra0, tmp_reg);
436 mtsdr(sdrultra0, tmp_reg | 0x04000000);
439 * set EPLD0_MUX_CTL.OESPR3 = 0
441 mtspr(SPRG7, LOAK_CRAM); /* "CRAM" */
442 } /* if (already_inited != 1) */
444 return (64 * 1024 * 1024);
448 * return 0 if not PSRAM
449 * return 1 if is PSRAM
451 static int is_psram(u32 addr)
453 u32 test_pattern = 0xdeadbeef;
454 volatile u32 readback;
456 if (addr == CFG_SDRAM_BASE) {
457 /* This is to temp enable OE for PSRAM */
458 out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f);
462 out32(addr, test_pattern);
463 asm volatile(" sync");
464 asm volatile(" eieio");
466 readback = (volatile u32) in32(addr);
467 asm volatile(" sync");
468 asm volatile(" eieio");
469 if (readback == test_pattern) {
476 static long int psram_init(void)
482 /* This is to temp enable OE for PSRAM */
483 out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f);
487 * PSRAM bank 1: read then write to address 0x00000000
489 for (i = 0; i < 100; i++) {
490 if (is_psram(CFG_SDRAM_BASE + (i*256)) == 1) {
491 readback = PSRAM_PASS;
493 readback = PSRAM_FAIL;
497 if (readback == PSRAM_PASS) {
498 debug("psram_init(bank0): pass\n");
499 psramsize = (16 * 1024 * 1024);
501 debug("psram_init(bank0): fail\n");
507 * PSRAM bank 1: read then write to address 0x01000000
509 for (i = 0; i < 100; i++) {
510 if (is_psram((1 << 24) + (i*256)) == 1) {
511 readback = PSRAM_PASS;
513 readback = PSRAM_FAIL;
517 if (readback == PSRAM_PASS) {
518 debug("psram_init(bank1): pass\n");
519 psramsize = psramsize + (16 * 1024 * 1024);
523 mtspr(SPRG7, LOAK_PSRAM); /* "PSRA" - PSRAM */
528 long int initdram(int board_type)
533 /* Determine Attached Memory Expansion Card*/
534 cram_inited = is_cram();
535 if (cram_inited != 0) { /* CRAM */
536 debug("CRAM Expansion Card attached\n");
537 sram_size = cram_init(cram_inited);
538 } else if (is_psram(CFG_SDRAM_BASE+4) == 1) { /* PSRAM */
539 debug("PSRAM Expansion Card attached\n");
540 sram_size = psram_init();
541 } else { /* no SRAM */
542 debug("No Memory Card Attached!!\n");