3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
27 extern void board_pll_init_f(void);
29 void liveoak_gpio_init(void)
32 * GPIO0 setup (select GPIO or alternate function)
34 out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
35 out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
36 out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
37 out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
38 out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
39 out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
40 out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
43 * Ultra (405EZ) was nice enough to add another GPIO controller
45 out32(GPIO1_OSRH, CFG_GPIO1_OSRH); /* output select */
46 out32(GPIO1_OSRL, CFG_GPIO1_OSRL);
47 out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H); /* input select */
48 out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L);
49 out32(GPIO1_TSRH, CFG_GPIO1_TSRH); /* three-state select */
50 out32(GPIO1_TSRL, CFG_GPIO1_TSRL);
51 out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */
54 int board_early_init_f(void)
61 /* USB Host core needs this bit set */
62 mfsdr(sdrultra1, reg);
63 mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
65 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
66 mtdcr(uicer, 0x00000000); /* disable all ints */
67 mtdcr(uiccr, 0x00000010);
68 mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */
69 mtdcr(uictr, 0x00000010); /* set int trigger levels */
70 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
77 /* Set EPLD to take PHY out of reset */
78 out8(CFG_CPLD_BASE + 0x05, 0x00);
85 * Check Board Identity:
89 char *s = getenv("serial#");
91 printf("Board: Acadia - AMCC PPC405EZ Evaluation Board");