3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
27 extern void board_pll_init_f(void);
29 /* Some specific Acadia Defines */
30 #define CPLD_BASE 0x80000000
32 void liveoak_gpio_init(void)
35 * GPIO0 setup (select GPIO or alternate function)
37 out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
38 out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
39 out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
40 out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
41 out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
42 out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
43 out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
46 * Ultra (405EZ) was nice enough to add another GPIO controller
48 out32(GPIO1_OSRH, CFG_GPIO1_OSRH); /* output select */
49 out32(GPIO1_OSRL, CFG_GPIO1_OSRL);
50 out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H); /* input select */
51 out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L);
52 out32(GPIO1_TSRH, CFG_GPIO1_TSRH); /* three-state select */
53 out32(GPIO1_TSRL, CFG_GPIO1_TSRL);
54 out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */
57 #if 0 /* test-only: not called at all??? */
58 void ext_bus_cntlr_init(void)
60 #if (defined(EBC_PB4AP) && defined(EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4))
61 mtebc(pb4ap, EBC_PB4AP);
62 mtebc(pb4cr, EBC_PB4CR);
67 int board_early_init_f(void)
73 * If CRAM memory and SPI/NAND boot, and if the CRAM memory is
74 * already initialized by the pre-loader then we can't reinitialize
75 * CPR registers, GPIO registers and EBC registers as this will
76 * have the effect of un-initializing CRAM.
78 spr_reg = (volatile unsigned long) mfspr(SPRG7);
79 if (spr_reg != LOAK_CRAM) { /* != CRAM */
84 mtebc(pb1ap, CFG_EBC_PB1AP);
85 mtebc(pb1cr, CFG_EBC_PB1CR);
87 mtebc(pb2ap, CFG_EBC_PB2AP);
88 mtebc(pb2cr, CFG_EBC_PB2CR);
93 /* ext_bus_cntlr_init(); */
96 #if 0 /* test-only (orig) */
98 * If we boot from NAND Flash, we are running in
99 * RAM, so disable the EBC_CS0 so that it goes back
100 * to the NOR Flash. It will be enabled later
101 * for the NAND Flash on EBC_CS1
103 mfsdr(sdrultra0, reg);
104 mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0);
106 #if 0 /* test-only */
107 /* configure for NAND */
108 mfsdr(sdrultra0, reg);
109 reg &= ~SDR_ULTRA0_CSN_MASK;
110 reg |= SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS;
111 mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0);
114 /* USB Host core needs this bit set */
115 mfsdr(sdrultra1, reg);
116 mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
118 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
119 mtdcr(uicer, 0x00000000); /* disable all ints */
120 mtdcr(uiccr, 0x00000010);
121 mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */
122 mtdcr(uictr, 0x00000010); /* set int trigger levels */
123 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
128 int misc_init_f(void)
130 /* Set EPLD to take PHY out of reset */
131 out8(CPLD_BASE + 0x05, 0x00);
138 * Check Board Identity:
142 char *s = getenv("serial#");
144 printf("Board: Acadia - AMCC PPC405EZ Evaluation Board");