2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
7 /* This file is autogenerated from tools provided by Altera.*/
8 #ifndef __SDRAM_CONFIG_H
9 #define __SDRAM_CONFIG_H
11 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
12 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
13 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
14 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
15 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
16 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
17 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
18 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
19 #define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
20 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
21 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
22 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
23 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
24 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19
25 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
26 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160
27 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8
28 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8
29 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8
30 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
31 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
32 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19
33 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26
34 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
35 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
36 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
37 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
38 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
39 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
40 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
41 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
42 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
43 #define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
44 #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
45 #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
46 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
47 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
48 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
49 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
50 #define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
51 #define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
52 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
53 #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
54 #define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
55 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
56 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
57 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
58 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
59 #define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
60 #define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
62 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
63 #define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
64 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
65 #define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
66 #define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
67 #define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
68 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
69 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
70 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
71 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
72 #define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
73 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \
75 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \
77 #define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \
79 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
80 #define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
81 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0
82 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0
83 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0
84 #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
86 #endif /*#ifndef__SDRAM_CONFIG_H*/