2 * Copyright (C) 2009 Texas Instruments Incorporated
5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/mtd/nand.h>
28 #include <asm/arch/hardware.h>
29 #include <asm/arch/nand_defs.h>
30 #include <asm/arch/davinci_misc.h>
31 #ifdef CONFIG_DAVINCI_MMC
33 #include <asm/arch/sdmmc_defs.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 #ifndef CONFIG_SPL_BUILD
39 static struct davinci_timer *timer =
40 (struct davinci_timer *)DAVINCI_TIMER3_BASE;
42 static unsigned long get_timer_val(void)
44 unsigned long now = readl(&timer->tim34);
49 static void stop_timer(void)
51 writel(0x0, &timer->tcr);
57 printf("Board: AIT CAM ENC 4XX\n");
63 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
68 #ifdef CONFIG_DRIVER_TI_EMAC
69 int board_eth_init(bd_t *bis)
71 davinci_emac_initialize();
77 #ifdef CONFIG_NAND_DAVINCI
79 davinci_std_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
80 uint8_t *buf, int page)
82 struct nand_chip *this = mtd->priv;
83 int i, eccsize = chip->ecc.size;
84 int eccbytes = chip->ecc.bytes;
85 int eccsteps = chip->ecc.steps;
87 uint8_t *oob = chip->oob_poi;
89 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
91 chip->read_buf(mtd, oob, mtd->oobsize);
93 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page & this->pagemask);
96 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
99 chip->ecc.hwctl(mtd, NAND_ECC_READ);
100 chip->read_buf(mtd, p, eccsize);
101 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
103 if (chip->ecc.prepad)
104 oob += chip->ecc.prepad;
106 stat = chip->ecc.correct(mtd, p, oob, NULL);
109 mtd->ecc_stats.failed++;
111 mtd->ecc_stats.corrected += stat;
115 if (chip->ecc.postpad)
116 oob += chip->ecc.postpad;
119 /* Calculate remaining oob bytes */
120 i = mtd->oobsize - (oob - chip->oob_poi);
122 chip->read_buf(mtd, oob, i);
127 static void davinci_std_write_page_syndrome(struct mtd_info *mtd,
128 struct nand_chip *chip, const uint8_t *buf)
130 unsigned char davinci_ecc_buf[NAND_MAX_OOBSIZE];
131 struct nand_chip *this = mtd->priv;
132 int i, eccsize = chip->ecc.size;
133 int eccbytes = chip->ecc.bytes;
134 int eccsteps = chip->ecc.steps;
135 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
137 const uint8_t *p = buf;
138 uint8_t *oob = chip->oob_poi;
140 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
141 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
142 chip->write_buf(mtd, p, eccsize);
144 /* Calculate ECC without prepad */
145 chip->ecc.calculate(mtd, p, oob + chip->ecc.prepad);
147 if (chip->ecc.prepad) {
148 offset = (chip->ecc.steps - eccsteps) * chunk;
149 memcpy(&davinci_ecc_buf[offset], oob, chip->ecc.prepad);
150 oob += chip->ecc.prepad;
153 offset = ((chip->ecc.steps - eccsteps) * chunk) +
155 memcpy(&davinci_ecc_buf[offset], oob, eccbytes);
158 if (chip->ecc.postpad) {
159 offset = ((chip->ecc.steps - eccsteps) * chunk) +
160 chip->ecc.prepad + eccbytes;
161 memcpy(&davinci_ecc_buf[offset], oob,
163 oob += chip->ecc.postpad;
168 * Write the sparebytes into the page once
169 * all eccsteps have been covered
171 for (i = 0; i < mtd->oobsize; i++)
172 writeb(davinci_ecc_buf[i], this->IO_ADDR_W);
174 /* Calculate remaining oob bytes */
175 i = mtd->oobsize - (oob - chip->oob_poi);
177 chip->write_buf(mtd, oob, i);
180 static int davinci_std_write_oob_syndrome(struct mtd_info *mtd,
181 struct nand_chip *chip, int page)
184 const uint8_t *bufpoi = chip->oob_poi;
186 pos = mtd->writesize;
188 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
190 chip->write_buf(mtd, bufpoi, mtd->oobsize);
192 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
193 status = chip->waitfunc(mtd, chip);
195 return status & NAND_STATUS_FAIL ? -1 : 0;
198 static int davinci_std_read_oob_syndrome(struct mtd_info *mtd,
199 struct nand_chip *chip, int page, int sndcmd)
201 struct nand_chip *this = mtd->priv;
202 uint8_t *buf = chip->oob_poi;
203 uint8_t *bufpoi = buf;
205 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask);
207 chip->read_buf(mtd, bufpoi, mtd->oobsize);
212 static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip)
214 struct nand_chip *this = mtd->priv;
215 unsigned long wbase = (unsigned long) this->IO_ADDR_W;
216 unsigned long rbase = (unsigned long) this->IO_ADDR_R;
219 __set_bit(14, &wbase);
220 __set_bit(14, &rbase);
222 __clear_bit(14, &wbase);
223 __clear_bit(14, &rbase);
225 this->IO_ADDR_W = (void *)wbase;
226 this->IO_ADDR_R = (void *)rbase;
229 int board_nand_init(struct nand_chip *nand)
231 davinci_nand_init(nand);
232 nand->select_chip = nand_dm365evm_select_chip;
237 struct nand_ecc_ctrl org_ecc;
238 static int notsaved = 1;
240 static int nand_switch_hw_func(int mode)
242 struct nand_chip *nand;
243 struct mtd_info *mtd;
245 if (nand_curr_device < 0 ||
246 nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
247 !nand_info[nand_curr_device].name) {
248 printf("Error: Can't switch hw functions," \
249 " no devices available\n");
253 mtd = &nand_info[nand_curr_device];
257 printf("switching to uboot hw functions.\n");
258 memcpy(&nand->ecc, &org_ecc, sizeof(struct nand_ecc_ctrl));
261 printf("switching to RBL hw functions.\n");
263 memcpy(&org_ecc, &nand->ecc,
264 sizeof(struct nand_ecc_ctrl));
267 nand->ecc.mode = NAND_ECC_HW_SYNDROME;
268 nand->ecc.prepad = 6;
269 nand->ecc.read_page = davinci_std_read_page_syndrome;
270 nand->ecc.write_page = davinci_std_write_page_syndrome;
271 nand->ecc.read_oob = davinci_std_read_oob_syndrome;
272 nand->ecc.write_oob = davinci_std_write_oob_syndrome;
279 static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
284 if (strncmp(argv[1], "rbl", 2) == 0)
285 hwmode = nand_switch_hw_func(1);
286 else if (strncmp(argv[1], "uboot", 2) == 0)
287 hwmode = nand_switch_hw_func(0);
294 printf("Usage: nandrbl %s\n", cmdtp->usage);
299 nandrbl, 2, 1, do_switch_ecc,
300 "switch between rbl/uboot NAND ECC calculation algorithm",
301 "[rbl/uboot] - Switch between rbl/uboot NAND ECC algorithm"
305 #endif /* #ifdef CONFIG_NAND_DAVINCI */
307 #ifdef CONFIG_DAVINCI_MMC
308 static struct davinci_mmc mmc_sd0 = {
309 .reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
310 .input_clk = 121500000,
311 .host_caps = MMC_MODE_4BIT,
312 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
313 .version = MMC_CTLR_VERSION_2,
316 int board_mmc_init(bd_t *bis)
320 /* Add slot-0 to mmc subsystem */
321 err = davinci_mmc_init(bis, &mmc_sd0);
327 int board_late_init(void)
329 struct davinci_gpio *gpio = davinci_gpio_bank45;
331 /* 24MHz InputClock / 15 prediv -> 1.6 MHz timer running */
332 while (get_timer_val() < 0x186a00)
335 /* 1 sec reached -> stop timer, clear all LED */
337 clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
343 char *name = "GENERIC @ 0x00";
346 miiphy_reset(name, 0x0);
349 #else /* #ifndef CONFIG_SPL_BUILD */
350 static void cam_enc_4xx_set_all_led(void)
352 struct davinci_gpio *gpio = davinci_gpio_bank45;
354 setbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
358 * TIMER 0 is used for tick
360 static struct davinci_timer *timer =
361 (struct davinci_timer *)DAVINCI_TIMER3_BASE;
363 #define TIMER_LOAD_VAL 0xffffffff
364 #define TIM_CLK_DIV 16
366 static int cam_enc_4xx_timer_init(void)
368 /* We are using timer34 in unchained 32-bit mode, full speed */
369 writel(0x0, &timer->tcr);
370 writel(0x0, &timer->tgcr);
371 writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr);
372 writel(0x0, &timer->tim34);
373 writel(TIMER_LOAD_VAL, &timer->prd34);
374 writel(2 << 22, &timer->tcr);
378 void board_gpio_init(void)
380 struct davinci_gpio *gpio;
382 cam_enc_4xx_set_all_led();
383 cam_enc_4xx_timer_init();
384 gpio = davinci_gpio_bank01;
385 clrbits_le32(&gpio->dir, ~0xfdfffffe);
386 /* clear LED D14 = GPIO25 */
387 clrbits_le32(&gpio->out_data, 0x02000000);
388 gpio = davinci_gpio_bank23;
389 clrbits_le32(&gpio->dir, ~0x5ff0afef);
390 /* set GPIO61 to 1 -> intern UART0 as Console */
391 setbits_le32(&gpio->out_data, 0x20000000);
393 * PHY out of reset GIO 50 = 1
394 * NAND WP off GIO 51 = 1
396 setbits_le32(&gpio->out_data, 0x000c0004);
397 gpio = davinci_gpio_bank45;
398 clrbits_le32(&gpio->dir, ~(0xdb2fffff) | CONFIG_CAM_ENC_LED_MASK);
408 clrbits_le32(&gpio->out_data, CONFIG_CAM_ENC_LED_MASK);
409 gpio = davinci_gpio_bank67;
410 clrbits_le32(&gpio->dir, ~0x000007ff);
414 * functions for the post memory test.
416 int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
418 *vstart = CONFIG_SYS_SDRAM_BASE;
419 *size = PHYS_SDRAM_1_SIZE;
424 void arch_memory_failure_handle(void)
426 cam_enc_4xx_set_all_led();
427 puts("mem failure\n");