2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/at91sam9260.h>
28 #include <asm/arch/at91sam9260_matrix.h>
29 #include <asm/arch/at91sam9_smc.h>
30 #include <asm/arch/at91_common.h>
31 #include <asm/arch/at91_pmc.h>
32 #include <asm/arch/at91_rstc.h>
33 #include <asm/arch/gpio.h>
35 #include <asm/arch/hardware.h>
36 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
41 DECLARE_GLOBAL_DATA_PTR;
43 /* ------------------------------------------------------------------------- */
45 * Miscelaneous platform dependent initialisations
48 static void afeb9260_nand_hw_init(void)
51 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
52 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
54 /* Assign CS3 to NAND/SmartMedia Interface */
55 csa = readl(&matrix->ebicsa);
56 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
57 writel(csa, &matrix->ebicsa);
59 /* Configure SMC CS3 for NAND/SmartMedia */
60 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
61 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
63 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
64 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
66 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
68 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
69 AT91_SMC_MODE_EXNW_DISABLE |
71 AT91_SMC_MODE_TDF_CYCLE(2),
74 /* Configure RDY/BSY */
75 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
77 /* Enable NandFlash */
78 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
82 static void afeb9260_macb_hw_init(void)
84 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
85 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
86 struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
90 /* Enable EMAC clock */
91 writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
96 * RXDV (PA17) => PHY normal mode (not Test mode)
97 * ERX0 (PA14) => PHY ADDR0
98 * ERX1 (PA15) => PHY ADDR1
99 * ERX2 (PA25) => PHY ADDR2
100 * ERX3 (PA26) => PHY ADDR3
101 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
103 * PHY has internal pull-down
105 writel(pin_to_mask(AT91_PIN_PA14) |
106 pin_to_mask(AT91_PIN_PA15) |
107 pin_to_mask(AT91_PIN_PA17) |
108 pin_to_mask(AT91_PIN_PA25) |
109 pin_to_mask(AT91_PIN_PA26) |
110 pin_to_mask(AT91_PIN_PA28),
113 erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
115 /* Need to reset PHY -> 500ms reset */
116 writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
117 AT91_RSTC_MR_URSTEN, &rstc->mr);
118 writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
120 /* Wait for end hardware reset */
121 while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
123 /* Restore NRST value */
124 writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
128 /* Re-enable pull-up */
129 writel(pin_to_mask(AT91_PIN_PA14) |
130 pin_to_mask(AT91_PIN_PA15) |
131 pin_to_mask(AT91_PIN_PA17) |
132 pin_to_mask(AT91_PIN_PA25) |
133 pin_to_mask(AT91_PIN_PA26) |
134 pin_to_mask(AT91_PIN_PA28),
140 int board_early_init_f(void)
142 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
143 /* Enable clocks for all PIOs */
144 writel((1 << ATMEL_ID_PIOA) |
145 (1 << ATMEL_ID_PIOB) |
146 (1 << ATMEL_ID_PIOC),
152 /* arch number of AT91SAM9260EK-Board */
153 gd->bd->bi_arch_number = MACH_TYPE_AFEB9260;
154 /* adress of boot parameters */
155 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
157 at91_seriald_hw_init();
158 #ifdef CONFIG_CMD_NAND
159 afeb9260_nand_hw_init();
161 at91_spi0_hw_init((1 << 0) | (1 << 1));
163 afeb9260_macb_hw_init();
171 gd->ram_size = get_ram_size(
172 (void *)CONFIG_SYS_SDRAM_BASE,
173 CONFIG_SYS_SDRAM_SIZE);
178 #ifdef CONFIG_RESET_PHY_R
184 int board_eth_init(bd_t *bis)
188 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x01);