board/advantech/dms-ba16/dms-ba16.c

   1 /*
   2  * Copyright 2016 Timesys Corporation
   3  * Copyright 2016 Advantech Corporation
   4  * Copyright 2012 Freescale Semiconductor, Inc.
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <linux/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/mach-imx/mxc_i2c.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/mach-imx/video.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <miiphy.h>
  22 #include <netdev.h>
  23 #include <asm/arch/mxc_hdmi.h>
  24 #include <asm/arch/crm_regs.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <i2c.h>
  28 #include <input.h>
  29 #include <pwm.h>
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |      \
  33         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  34         PAD_CTL_HYS)
  35
  36 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  37         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  38         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  41         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  42         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
  45         PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  46
  47 #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  48         PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  49
  50 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  51         PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
  52
  53 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  54                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  55
  56 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  57         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  58         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  59
  60 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  61
  62 int dram_init(void)
  63 {
  64         gd->ram_size = imx_ddr_size();
  65
  66         return 0;
  67 }
  68
  69 static iomux_v3_cfg_t const uart3_pads[] = {
  70         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  71         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  72         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  73         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  74 };
  75
  76 static iomux_v3_cfg_t const uart4_pads[] = {
  77         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  78         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  79 };
  80
  81 static iomux_v3_cfg_t const enet_pads[] = {
  82         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83         MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84         MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85         MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86         MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87         MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88         MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  91         MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  92         MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  93         MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  94         MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  95         MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  96         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  97         /* AR8033 PHY Reset */
  98         MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  99 };
 100
 101 static void setup_iomux_enet(void)
 102 {
 103         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 104
 105         /* Reset AR8033 PHY */
 106         gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
 107         mdelay(10);
 108         gpio_set_value(IMX_GPIO_NR(1, 28), 1);
 109         mdelay(1);
 110 }
 111
 112 static iomux_v3_cfg_t const usdhc2_pads[] = {
 113         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 114         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX6_PAD_GPIO_4__GPIO1_IO04      | MUX_PAD_CTRL(NO_PAD_CTRL),
 120 };
 121
 122 static iomux_v3_cfg_t const usdhc3_pads[] = {
 123         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 124         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 125         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 126         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 127         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 128         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 129         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 130         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 131         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134 };
 135
 136 static iomux_v3_cfg_t const usdhc4_pads[] = {
 137         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 147         MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
 148         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
 149 };
 150
 151 static iomux_v3_cfg_t const ecspi1_pads[] = {
 152         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 153         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 154         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 155         MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
 156 };
 157
 158 static struct i2c_pads_info i2c_pad_info1 = {
 159         .scl = {
 160                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
 161                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
 162                 .gp = IMX_GPIO_NR(5, 27)
 163         },
 164         .sda = {
 165                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
 166                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
 167                 .gp = IMX_GPIO_NR(5, 26)
 168         }
 169 };
 170
 171 static struct i2c_pads_info i2c_pad_info2 = {
 172         .scl = {
 173                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
 174                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 175                 .gp = IMX_GPIO_NR(4, 12)
 176         },
 177         .sda = {
 178                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 179                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 180                 .gp = IMX_GPIO_NR(4, 13)
 181         }
 182 };
 183
 184 static struct i2c_pads_info i2c_pad_info3 = {
 185         .scl = {
 186                 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
 187                 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
 188                 .gp = IMX_GPIO_NR(1, 3)
 189         },
 190         .sda = {
 191                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
 192                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
 193                 .gp = IMX_GPIO_NR(1, 6)
 194         }
 195 };
 196
 197 #ifdef CONFIG_MXC_SPI
 198 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 199 {
 200         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
 201 }
 202
 203 static void setup_spi(void)
 204 {
 205         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 206 }
 207 #endif
 208
 209 static iomux_v3_cfg_t const pcie_pads[] = {
 210         MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 211         MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 212 };
 213
 214 static void setup_pcie(void)
 215 {
 216         imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 217 }
 218
 219 static void setup_iomux_uart(void)
 220 {
 221         imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
 222         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 223 }
 224
 225 #ifdef CONFIG_FSL_ESDHC
 226 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 227         {USDHC2_BASE_ADDR},
 228         {USDHC3_BASE_ADDR},
 229         {USDHC4_BASE_ADDR},
 230 };
 231
 232 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 233 #define USDHC4_CD_GPIO  IMX_GPIO_NR(6, 11)
 234
 235 int board_mmc_getcd(struct mmc *mmc)
 236 {
 237         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 238         int ret = 0;
 239
 240         switch (cfg->esdhc_base) {
 241         case USDHC2_BASE_ADDR:
 242                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 243                 break;
 244         case USDHC3_BASE_ADDR:
 245                 ret = 1; /* eMMC is always present */
 246                 break;
 247         case USDHC4_BASE_ADDR:
 248                 ret = !gpio_get_value(USDHC4_CD_GPIO);
 249                 break;
 250         }
 251
 252         return ret;
 253 }
 254
 255 int board_mmc_init(bd_t *bis)
 256 {
 257         int ret;
 258         int i;
 259
 260         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 261                 switch (i) {
 262                 case 0:
 263                         imx_iomux_v3_setup_multiple_pads(
 264                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 265                         gpio_direction_input(USDHC2_CD_GPIO);
 266                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 267                         break;
 268                 case 1:
 269                         imx_iomux_v3_setup_multiple_pads(
 270                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 271                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 272                         break;
 273                 case 2:
 274                         imx_iomux_v3_setup_multiple_pads(
 275                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 276                         gpio_direction_input(USDHC4_CD_GPIO);
 277                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 278                         break;
 279                 default:
 280                         printf("Warning: you configured more USDHC controllers\n"
 281                                "(%d) then supported by the board (%d)\n",
 282                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 283                         return -EINVAL;
 284                 }
 285
 286                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 287                 if (ret)
 288                         return ret;
 289         }
 290
 291         return 0;
 292 }
 293 #endif
 294
 295 static int mx6_rgmii_rework(struct phy_device *phydev)
 296 {
 297         /* set device address 0x7 */
 298         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 299         /* offset 0x8016: CLK_25M Clock Select */
 300         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 301         /* enable register write, no post increment, address 0x7 */
 302         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 303         /* set to 125 MHz from local PLL source */
 304         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
 305         /* set debug port address: SerDes Test and System Mode Control */
 306         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
 307         /* enable rgmii tx clock delay */
 308         /* set the reserved bits to avoid board specific voltage peak issue*/
 309         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
 310
 311         return 0;
 312 }
 313
 314 int board_phy_config(struct phy_device *phydev)
 315 {
 316         mx6_rgmii_rework(phydev);
 317
 318         if (phydev->drv->config)
 319                 phydev->drv->config(phydev);
 320
 321         return 0;
 322 }
 323
 324 #if defined(CONFIG_VIDEO_IPUV3)
 325 static iomux_v3_cfg_t const backlight_pads[] = {
 326         /* Power for LVDS Display */
 327         MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
 328 #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
 329         /* Backlight enable for LVDS display */
 330         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 331 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
 332         /* backlight PWM brightness control */
 333         MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 334 };
 335
 336 static void do_enable_hdmi(struct display_info_t const *dev)
 337 {
 338         imx_enable_hdmi_phy();
 339 }
 340
 341 int board_cfb_skip(void)
 342 {
 343         gpio_direction_output(LVDS_POWER_GP, 1);
 344
 345         return 0;
 346 }
 347
 348 static int detect_baseboard(struct display_info_t const *dev)
 349 {
 350         return 0 == dev->addr;
 351 }
 352
 353 struct display_info_t const displays[] = {{
 354         .bus    = -1,
 355         .addr   = 0,
 356         .pixfmt = IPU_PIX_FMT_RGB24,
 357         .detect = detect_baseboard,
 358         .enable = NULL,
 359         .mode   = {
 360                 .name           = "SHARP-LQ156M1LG21",
 361                 .refresh        = 60,
 362                 .xres           = 1920,
 363                 .yres           = 1080,
 364                 .pixclock       = 7851,
 365                 .left_margin    = 100,
 366                 .right_margin   = 40,
 367                 .upper_margin   = 30,
 368                 .lower_margin   = 3,
 369                 .hsync_len      = 10,
 370                 .vsync_len      = 2,
 371                 .sync           = FB_SYNC_EXT,
 372                 .vmode          = FB_VMODE_NONINTERLACED
 373 } }, {
 374         .bus    = -1,
 375         .addr   = 3,
 376         .pixfmt = IPU_PIX_FMT_RGB24,
 377         .detect = detect_hdmi,
 378         .enable = do_enable_hdmi,
 379         .mode   = {
 380                 .name           = "HDMI",
 381                 .refresh        = 60,
 382                 .xres           = 1024,
 383                 .yres           = 768,
 384                 .pixclock       = 15385,
 385                 .left_margin    = 220,
 386                 .right_margin   = 40,
 387                 .upper_margin   = 21,
 388                 .lower_margin   = 7,
 389                 .hsync_len      = 60,
 390                 .vsync_len      = 10,
 391                 .sync           = FB_SYNC_EXT,
 392                 .vmode          = FB_VMODE_NONINTERLACED
 393 } } };
 394 size_t display_count = ARRAY_SIZE(displays);
 395
 396 static void setup_display(void)
 397 {
 398         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 399         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 400
 401         clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
 402
 403         imx_setup_hdmi();
 404
 405         /* Set LDB_DI0 as clock source for IPU_DI0 */
 406         clrsetbits_le32(&mxc_ccm->chsccdr,
 407                         MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
 408                         (CHSCCDR_CLK_SEL_LDB_DI0 <<
 409                          MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
 410
 411         /* Turn on IPU LDB DI0 clocks */
 412         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
 413
 414         enable_ipu_clock();
 415
 416         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
 417                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
 418                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
 419                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
 420                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
 421                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
 422                IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 423                IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
 424                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
 425                IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
 426                &iomux->gpr[2]);
 427
 428         clrsetbits_le32(&iomux->gpr[3],
 429                         IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
 430                         IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
 431                         IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
 432                        (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 433                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
 434
 435         /* backlights off until needed */
 436         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 437                                          ARRAY_SIZE(backlight_pads));
 438
 439         gpio_direction_input(LVDS_POWER_GP);
 440         gpio_direction_input(LVDS_BACKLIGHT_GP);
 441 }
 442 #endif /* CONFIG_VIDEO_IPUV3 */
 443
 444 /*
 445  * Do not overwrite the console
 446  * Use always serial for U-Boot console
 447  */
 448 int overwrite_console(void)
 449 {
 450         return 1;
 451 }
 452
 453 int board_eth_init(bd_t *bis)
 454 {
 455         setup_iomux_enet();
 456         setup_pcie();
 457
 458         return cpu_eth_init(bis);
 459 }
 460
 461 static iomux_v3_cfg_t const misc_pads[] = {
 462         MX6_PAD_KEY_ROW2__GPIO4_IO11    | MUX_PAD_CTRL(NO_PAD_CTRL),
 463         MX6_PAD_EIM_A25__GPIO5_IO02     | MUX_PAD_CTRL(NC_PAD_CTRL),
 464         MX6_PAD_EIM_CS0__GPIO2_IO23     | MUX_PAD_CTRL(NC_PAD_CTRL),
 465         MX6_PAD_EIM_CS1__GPIO2_IO24     | MUX_PAD_CTRL(NC_PAD_CTRL),
 466         MX6_PAD_EIM_OE__GPIO2_IO25      | MUX_PAD_CTRL(NC_PAD_CTRL),
 467         MX6_PAD_EIM_BCLK__GPIO6_IO31    | MUX_PAD_CTRL(NC_PAD_CTRL),
 468         MX6_PAD_GPIO_1__GPIO1_IO01      | MUX_PAD_CTRL(NC_PAD_CTRL),
 469 };
 470 #define SUS_S3_OUT      IMX_GPIO_NR(4, 11)
 471 #define WIFI_EN IMX_GPIO_NR(6, 14)
 472
 473 int setup_ba16_sata(void)
 474 {
 475         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 476         int ret;
 477
 478         ret = enable_sata_clock();
 479         if (ret)
 480                 return ret;
 481
 482         clrsetbits_le32(&iomuxc_regs->gpr[13],
 483                         IOMUXC_GPR13_SATA_MASK,
 484                         IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
 485                         |IOMUXC_GPR13_SATA_PHY_7_SATA2M
 486                         |IOMUXC_GPR13_SATA_SPEED_3G
 487                         |(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
 488                         |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
 489                         |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
 490                         |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
 491                         |IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
 492                         |IOMUXC_GPR13_SATA_PHY_1_SLOW);
 493
 494         return 0;
 495 }
 496
 497 int board_early_init_f(void)
 498 {
 499         imx_iomux_v3_setup_multiple_pads(misc_pads,
 500                                          ARRAY_SIZE(misc_pads));
 501
 502         setup_iomux_uart();
 503
 504 #if defined(CONFIG_VIDEO_IPUV3)
 505         /* Set LDB clock to PLL2 PFD0 */
 506         select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK);
 507 #endif
 508         return 0;
 509 }
 510
 511 int board_init(void)
 512 {
 513         gpio_direction_output(SUS_S3_OUT, 1);
 514         gpio_direction_output(WIFI_EN, 1);
 515 #if defined(CONFIG_VIDEO_IPUV3)
 516         setup_display();
 517 #endif
 518         /* address of boot parameters */
 519         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 520
 521 #ifdef CONFIG_MXC_SPI
 522         setup_spi();
 523 #endif
 524         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 525         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 526         setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
 527
 528         return 0;
 529 }
 530
 531 #ifdef CONFIG_CMD_BMODE
 532 static const struct boot_mode board_boot_modes[] = {
 533         /* 4 bit bus width */
 534         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 535         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 536         {NULL,   0},
 537 };
 538 #endif
 539
 540 void pmic_init(void)
 541 {
 542
 543 #define DA9063_ADDR 0x58
 544 #define BCORE2_CONF 0x9D
 545 #define BCORE1_CONF 0x9E
 546 #define BPRO_CONF 0x9F
 547 #define BIO_CONF 0xA0
 548 #define BMEM_CONF 0xA1
 549 #define BPERI_CONF 0xA2
 550 #define MODE_BIT_H 7
 551 #define MODE_BIT_L 6
 552
 553         uchar val;
 554         i2c_set_bus_num(2);
 555
 556         i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1);
 557         val |= (1 << MODE_BIT_H);
 558         val &= ~(1 << MODE_BIT_L);
 559         i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1);
 560
 561         i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1);
 562         val |= (1 << MODE_BIT_H);
 563         val &= ~(1 << MODE_BIT_L);
 564         i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1);
 565
 566         i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1);
 567         val |= (1 << MODE_BIT_H);
 568         val &= ~(1 << MODE_BIT_L);
 569         i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1);
 570
 571         i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1);
 572         val |= (1 << MODE_BIT_H);
 573         val &= ~(1 << MODE_BIT_L);
 574         i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1);
 575
 576         i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1);
 577         val |= (1 << MODE_BIT_H);
 578         val &= ~(1 << MODE_BIT_L);
 579         i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1);
 580
 581         i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1);
 582         val |= (1 << MODE_BIT_H);
 583         val &= ~(1 << MODE_BIT_L);
 584         i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1);
 585
 586 }
 587
 588 int board_late_init(void)
 589 {
 590 #ifdef CONFIG_CMD_BMODE
 591         add_board_boot_modes(board_boot_modes);
 592 #endif
 593
 594 #if defined(CONFIG_VIDEO_IPUV3)
 595         /*
 596          * We need at least 200ms between power on and backlight on
 597          * as per specifications from CHI MEI
 598          */
 599         mdelay(250);
 600
 601         /* enable backlight PWM 1 */
 602         pwm_init(0, 0, 0);
 603
 604         /* duty cycle 5000000ns, period: 5000000ns */
 605         pwm_config(0, 5000000, 5000000);
 606
 607         /* Backlight Power */
 608         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 609
 610         pwm_enable(0);
 611 #endif
 612
 613 #ifdef CONFIG_SATA
 614         setup_ba16_sata();
 615 #endif
 616
 617         /* board specific pmic init */
 618         pmic_init();
 619
 620         return 0;
 621 }
 622
 623 int checkboard(void)
 624 {
 625         printf("BOARD: %s\n", CONFIG_BOARD_NAME);
 626         return 0;
 627 }