3 * Martha J Marx, Silicon Turnkey Express, mmarx@silicontkx.com
4 * mpc512x I/O pin/pad initialization for the ADS5121 board
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/types.h>
29 #define IO_PIN_FMUX(v) ((v) << 7) /* pin function */
30 #define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */
31 #define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */
32 #define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */
33 #define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */
34 #define IO_PIN_DS(v) ((v)) /* slew rate */
36 static struct iopin_t {
37 int p_offset; /* offset from IOCTL_MEM_OFFSET */
38 int nr_pins; /* number of pins to set this way */
39 int bit_or; /* or in the value instead of overwrite */
40 u_long val; /* value to write or or */
42 /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
44 IOCTL_SPDIF_TXCLK, 3, 0,
45 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
46 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
48 /* Set highest Slew on 9 PATA pins */
51 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
52 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
54 /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
57 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
58 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
60 /* FUNC1=SPDIF_TXCLK */
63 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
64 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
66 /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
69 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
70 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
75 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
76 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
81 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
82 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
84 /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
87 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
88 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
92 void iopin_initialize(void)
96 immap_t *im = (immap_t *)CFG_IMMR;
98 reg = (u_long *)&(im->io_ctrl.regs[0]);
100 if (sizeof(ioregs_init) == 0)
103 n = sizeof(ioregs_init) / sizeof(ioregs_init[0]);
105 for (i = 0; i < n; i++) {
106 for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
107 p < ioregs_init[i].nr_pins; p++, j++) {
108 if (ioregs_init[i].bit_or)
109 reg[j] |= ioregs_init[i].val;
111 reg[j] = ioregs_init[i].val;