2 * (C) Copyright 2007 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/bitops.h>
28 #include <fdt_support.h>
31 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
32 CLOCK_SCCR1_LPC_EN | \
33 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
34 CLOCK_SCCR1_PSCFIFO_EN | \
35 CLOCK_SCCR1_DDR_EN | \
36 CLOCK_SCCR1_FEC_EN | \
37 CLOCK_SCCR1_PCI_EN | \
40 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
41 CLOCK_SCCR2_SPDIF_EN | \
42 CLOCK_SCCR2_DIU_EN | \
45 #define CSAW_START(start) ((start) & 0xFFFF0000)
46 #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
48 #define MPC5121_IOCTL_PSC6_0 (0x284/4)
49 #define MPC5121_IO_DIU_START (0x288/4)
50 #define MPC5121_IO_DIU_END (0x2fc/4)
52 /* Functional pin muxing */
53 #define MPC5121_IO_FUNC1 (0 << 7)
54 #define MPC5121_IO_FUNC2 (1 << 7)
55 #define MPC5121_IO_FUNC3 (2 << 7)
56 #define MPC5121_IO_FUNC4 (3 << 7)
57 #define MPC5121_IO_ST (1 << 2)
58 #define MPC5121_IO_DS_1 (0)
59 #define MPC5121_IO_DS_2 (1)
60 #define MPC5121_IO_DS_3 (2)
61 #define MPC5121_IO_DS_4 (3)
63 long int fixed_sdram(void);
65 int board_early_init_f (void)
67 volatile immap_t *im = (immap_t *) CFG_IMMR;
69 volatile ioctrl512x_t *ioctl = &(im->io_ctrl);
73 * Initialize Local Window for the CPLD registers access (CS2 selects
76 im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
77 CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
78 im->lpc.cs_cfg[2] = CFG_CS2_CFG;
81 * According to MPC5121e RM, configuring local access windows should
82 * be followed by a dummy read of the config register that was
83 * modified last and an isync
85 lpcaw = im->sysconf.lpcs2aw;
86 __asm__ __volatile__ ("isync");
89 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
91 * Without this the flash identification routine fails, as it needs to issue
92 * write commands in order to establish the device ID.
94 *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
99 im->clk.sccr[0] = SCCR1_CLOCKS_EN;
100 im->clk.sccr[1] = SCCR2_CLOCKS_EN;
102 /* Configure DIU clock pin */
103 tmp32 = ioctl->regs[MPC5121_IOCTL_PSC6_0];
105 tmp32 |= MPC5121_IO_FUNC3 | MPC5121_IO_DS_4;
106 ioctl->regs[MPC5121_IOCTL_PSC6_0] = tmp32;
108 /* Initialize IO pins (pin mux) for DIU function */
109 for (i = MPC5121_IO_DIU_START; i < MPC5121_IO_DIU_END; i++)
110 ioctl->regs[i] |= (MPC5121_IO_FUNC3 | MPC5121_IO_DS_4);
115 long int initdram (int board_type)
119 msize = fixed_sdram ();
125 * fixed sdram init -- the board doesn't use memory modules that have serial presence
126 * detect or similar mechanism for discovery of the DRAM settings
128 long int fixed_sdram (void)
130 volatile immap_t *im = (immap_t *) CFG_IMMR;
131 u32 msize = CFG_DDR_SIZE * 1024 * 1024;
132 u32 msize_log2 = __ilog2 (msize);
135 /* Initialize IO Control */
136 im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;
138 /* Initialize DDR Local Window */
139 im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
140 im->sysconf.ddrlaw.ar = msize_log2 - 1;
143 * According to MPC5121e RM, configuring local access windows should
144 * be followed by a dummy read of the config register that was
145 * modified last and an isync
147 i = im->sysconf.ddrlaw.ar;
148 __asm__ __volatile__ ("isync");
151 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;
153 /* Initialize DDR Priority Manager */
154 im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
155 im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
156 im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
157 im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
158 im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
159 im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
160 im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
161 im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
162 im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
163 im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
164 im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
165 im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
166 im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
167 im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
168 im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL;
169 im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
170 im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
171 im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
172 im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
173 im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
174 im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
175 im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
176 im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
178 /* Initialize MDDRC */
179 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
180 im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
181 im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
182 im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;
185 for (i = 0; i < 10; i++)
186 im->mddrc.ddr_command = CFG_MICRON_NOP;
188 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
189 im->mddrc.ddr_command = CFG_MICRON_NOP;
190 im->mddrc.ddr_command = CFG_MICRON_RFSH;
191 im->mddrc.ddr_command = CFG_MICRON_NOP;
192 im->mddrc.ddr_command = CFG_MICRON_RFSH;
193 im->mddrc.ddr_command = CFG_MICRON_NOP;
194 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
195 im->mddrc.ddr_command = CFG_MICRON_NOP;
196 im->mddrc.ddr_command = CFG_MICRON_EM2;
197 im->mddrc.ddr_command = CFG_MICRON_NOP;
198 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
199 im->mddrc.ddr_command = CFG_MICRON_EM2;
200 im->mddrc.ddr_command = CFG_MICRON_EM3;
201 im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
202 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
203 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
204 im->mddrc.ddr_command = CFG_MICRON_RFSH;
205 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
206 im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
207 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
208 im->mddrc.ddr_command = CFG_MICRON_NOP;
211 im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
212 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;
217 int misc_init_r(void)
221 /* Using this for DIU init before the driver in linux takes over
222 * Enable the TFP410 Encoder (I2C address 0x38)
227 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
228 /* Verify if enabled */
230 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
231 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
234 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
235 /* Verify if enabled */
237 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
238 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
240 #ifdef CONFIG_FSL_DIU_FB
241 #if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
249 int checkboard (void)
251 ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
252 uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
253 volatile immap_t *im = (immap_t *) CFG_IMMR;
254 volatile unsigned long *reg;
257 printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
260 /* change the slew rate on all pata pins to max */
261 reg = (unsigned long *) &(im->io_ctrl.regs[PATA_CE1_IDX]);
262 for (i = 0; i < 9; i++)
263 reg[i] |= 0x00000003;
267 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
268 void ft_board_setup(void *blob, bd_t *bd)
270 ft_cpu_setup(blob, bd);
271 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
273 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */