2 * (C) Copyright 2007 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/bitops.h>
28 #include <fdt_support.h>
29 #ifdef CONFIG_MISC_INIT_R
33 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
34 CLOCK_SCCR1_LPC_EN | \
35 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
36 CLOCK_SCCR1_PSCFIFO_EN | \
37 CLOCK_SCCR1_DDR_EN | \
38 CLOCK_SCCR1_FEC_EN | \
39 CLOCK_SCCR1_PCI_EN | \
42 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
43 CLOCK_SCCR2_SPDIF_EN | \
44 CLOCK_SCCR2_DIU_EN | \
47 #define CSAW_START(start) ((start) & 0xFFFF0000)
48 #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
50 long int fixed_sdram(void);
52 int board_early_init_f (void)
54 volatile immap_t *im = (immap_t *) CFG_IMMR;
59 * Initialize Local Window for the CPLD registers access (CS2 selects
62 im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
63 CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
64 im->lpc.cs_cfg[2] = CFG_CS2_CFG;
67 * According to MPC5121e RM, configuring local access windows should
68 * be followed by a dummy read of the config register that was
69 * modified last and an isync
71 lpcaw = im->sysconf.lpcs2aw;
72 __asm__ __volatile__ ("isync");
75 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
77 * Without this the flash identification routine fails, as it needs to issue
78 * write commands in order to establish the device ID.
81 #ifdef CONFIG_ADS5121_REV2
82 *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
84 if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) {
85 *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
87 /* running from Backup flash */
88 *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32;
92 * Configure Flash Speed
94 *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG;
98 im->clk.sccr[0] = SCCR1_CLOCKS_EN;
99 im->clk.sccr[1] = SCCR2_CLOCKS_EN;
104 phys_size_t initdram (int board_type)
108 msize = fixed_sdram ();
114 * fixed sdram init -- the board doesn't use memory modules that have serial presence
115 * detect or similar mechanism for discovery of the DRAM settings
117 long int fixed_sdram (void)
119 volatile immap_t *im = (immap_t *) CFG_IMMR;
120 u32 msize = CFG_DDR_SIZE * 1024 * 1024;
121 u32 msize_log2 = __ilog2 (msize);
124 /* Initialize IO Control */
125 im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR;
127 /* Initialize DDR Local Window */
128 im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
129 im->sysconf.ddrlaw.ar = msize_log2 - 1;
132 * According to MPC5121e RM, configuring local access windows should
133 * be followed by a dummy read of the config register that was
134 * modified last and an isync
136 i = im->sysconf.ddrlaw.ar;
137 __asm__ __volatile__ ("isync");
140 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;
142 /* Initialize DDR Priority Manager */
143 im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
144 im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
145 im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
146 im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
147 im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
148 im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
149 im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
150 im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
151 im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
152 im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
153 im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
154 im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
155 im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
156 im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
157 im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL;
158 im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
159 im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
160 im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
161 im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
162 im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
163 im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
164 im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
165 im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
167 /* Initialize MDDRC */
168 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
169 im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
170 im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
171 im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;
174 for (i = 0; i < 10; i++)
175 im->mddrc.ddr_command = CFG_MICRON_NOP;
177 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
178 im->mddrc.ddr_command = CFG_MICRON_NOP;
179 im->mddrc.ddr_command = CFG_MICRON_RFSH;
180 im->mddrc.ddr_command = CFG_MICRON_NOP;
181 im->mddrc.ddr_command = CFG_MICRON_RFSH;
182 im->mddrc.ddr_command = CFG_MICRON_NOP;
183 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
184 im->mddrc.ddr_command = CFG_MICRON_NOP;
185 im->mddrc.ddr_command = CFG_MICRON_EM2;
186 im->mddrc.ddr_command = CFG_MICRON_NOP;
187 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
188 im->mddrc.ddr_command = CFG_MICRON_EM2;
189 im->mddrc.ddr_command = CFG_MICRON_EM3;
190 im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
191 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
192 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
193 im->mddrc.ddr_command = CFG_MICRON_RFSH;
194 im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
195 im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
196 im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
197 im->mddrc.ddr_command = CFG_MICRON_NOP;
200 im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
201 im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;
206 int misc_init_r(void)
210 /* Using this for DIU init before the driver in linux takes over
211 * Enable the TFP410 Encoder (I2C address 0x38)
216 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
217 /* Verify if enabled */
219 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
220 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
223 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
224 /* Verify if enabled */
226 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
227 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
229 #ifdef CONFIG_FSL_DIU_FB
230 #if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
238 int checkboard (void)
240 ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
241 uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
243 printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
245 /* initialize function mux & slew rate IO inter alia on IO Pins */
251 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
252 void ft_board_setup(void *blob, bd_t *bd)
254 ft_cpu_setup(blob, bd);
255 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
257 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */