3 * Michael Schwingen, michael@schwingen.org
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13 * Marius Groeger <mgroeger@sysgo.de>
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/arch/ixp425.h>
42 #include <asm/arch/ixp425pci.h>
45 #include "actux1_hw.h"
47 DECLARE_GLOBAL_DATA_PTR;
49 int board_early_init_f(void)
52 writel(0x9d520003, IXP425_EXP_CS5);
54 writel(0x81860001, IXP425_EXP_CS6);
56 writel(0x80900003, IXP425_EXP_CS7);
62 gd->bd->bi_arch_number = MACH_TYPE_ACTUX1;
64 /* adress of boot parameters */
65 gd->bd->bi_boot_params = 0x00000100;
67 GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST);
68 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST);
70 /* Setup GPIOs for PCI INTA */
71 GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI1_INTA);
72 GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI1_INTA);
74 /* Setup GPIOs for 33MHz clock output */
75 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
76 GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
77 writel(0x011001FF, IXP425_GPIO_GPCLKR);
80 GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST);
90 ACTUX1_HS(ACTUX1_HS_DCD);
96 * Check Board Identity
101 int i = getenv_f("serial#", buf, sizeof(buf));
103 puts("Board: AcTux-1 rev.");
104 putc(ACTUX1_BOARDREL + 'A' - 1);
115 /*************************************************************************
116 * get_board_rev() - setup to pass kernel board revision information
120 *************************************************************************/
121 u32 get_board_rev(void)
123 return ACTUX1_BOARDREL;
128 gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20);
134 struct pci_controller hose;
136 void pci_init_board(void)
146 /* initialize the PHY */
147 miiphy_reset("NPE0", CONFIG_PHY_ADDR);
149 miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID1, &id1);
150 miiphy_read("NPE0", CONFIG_PHY_ADDR, MII_PHYSID2, &id2);
152 id2 &= 0xFFF0; /* mask out revision bits */
154 if (id1 == 0x13 && id2 == 0x78e0) {
156 * LXT971/LXT972 PHY: set LED outputs:
157 * LED1(green) = Link/ACT,
158 * LED2 (unused) = LINK,
161 miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
162 } else if (id1 == 0x143 && id2 == 0xbc30) {
163 /* BCM5241: default values are OK */
165 printf("unknown ethernet PHY ID: %x %x\n", id1, id2);