3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
9 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
11 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/processor.h>
21 #include <led-display.h>
22 #include <linux/err.h>
24 #include "mt46v32m16.h"
26 DECLARE_GLOBAL_DATA_PTR;
28 #ifndef CONFIG_SYS_RAMBOOT
29 static void sdram_start (int hi_addr)
31 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
32 long control = SDRAM_CONTROL | hi_addr_bit;
34 /* unlock mode register */
35 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
36 __asm__ volatile ("sync");
38 /* precharge all banks */
39 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
40 __asm__ volatile ("sync");
43 /* set mode register: extended mode */
44 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
45 __asm__ volatile ("sync");
47 /* set mode register: reset DLL */
48 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
49 __asm__ volatile ("sync");
52 /* precharge all banks */
53 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
54 __asm__ volatile ("sync");
57 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
58 __asm__ volatile ("sync");
60 /* set mode register */
61 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
62 __asm__ volatile ("sync");
64 /* normal operation */
65 out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
66 __asm__ volatile ("sync");
71 * ATTENTION: Although partially referenced initdram does NOT make real use
72 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
73 * is something else than 0x00000000.
81 #ifndef CONFIG_SYS_RAMBOOT
84 /* setup SDRAM chip selects */
85 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
86 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
87 __asm__ volatile ("sync");
89 /* setup config registers */
90 out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
91 out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
92 __asm__ volatile ("sync");
96 out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
97 __asm__ volatile ("sync");
100 /* find RAM size using SDRAM CS0 only */
102 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
104 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
112 /* memory smaller than 1MB is impossible */
113 if (dramsize < (1 << 20)) {
117 /* set SDRAM CS0 size according to the amount of RAM found */
119 out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
120 0x13 + __builtin_ffs(dramsize >> 20) - 1);
122 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
125 #else /* CONFIG_SYS_RAMBOOT */
127 /* retrieve size of memory connected to SDRAM CS0 */
128 dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
129 if (dramsize >= 0x13) {
130 dramsize = (1 << (dramsize - 0x13)) << 20;
135 #endif /* CONFIG_SYS_RAMBOOT */
138 * On MPC5200B we need to set the special configuration delay in the
139 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
140 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
142 * "The SDelay should be written to a value of 0x00000004. It is
143 * required to account for changes caused by normal wafer processing
148 if ((SVR_MJREV(svr) >= 2) &&
149 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
151 out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
152 __asm__ volatile ("sync");
155 gd->ram_size = dramsize;
160 int checkboard (void)
162 puts ("Board: A4M072\n");
167 static struct pci_controller hose;
169 extern void pci_mpc5xxx_init(struct pci_controller *);
171 void pci_init_board(void)
173 pci_mpc5xxx_init(&hose);
177 #ifdef CONFIG_OF_BOARD_SETUP
178 int ft_board_setup(void *blob, bd_t *bd)
180 ft_cpu_setup(blob, bd);
184 #endif /* CONFIG_OF_BOARD_SETUP */
186 int board_eth_init(bd_t *bis)
190 /* Initialize TSECs first */
191 if ((rv = cpu_eth_init(bis)) >= 0)
194 printf("ERROR: failed to initialize FEC.\n");
196 if ((rv = pci_eth_init(bis)) >= 0)
199 printf("ERROR: failed to initialize PCI Ethernet.\n");
204 * Miscellaneous late-boot configurations
206 * Initialize EEPROM write-protect GPIO pin.
208 int misc_init_r(void)
210 #if defined(CONFIG_SYS_EEPROM_WREN)
211 /* Enable GPIO pin */
212 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
213 /* Set direction, output */
214 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
215 /* De-assert write enable */
216 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
220 #if defined(CONFIG_SYS_EEPROM_WREN)
221 /* Input: <dev_addr> I2C address of EEPROM device to enable.
222 * <state> -1: deliver current state
225 * Returns: -1: wrong device address
226 * 0: dis-/en- able done
227 * 0/1: current state if <state> was -1.
229 int eeprom_write_enable (unsigned dev_addr, int state)
231 if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
236 /* Enable write access */
237 clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
241 /* Disable write access */
242 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
246 /* Read current status back. */
247 state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
248 CONFIG_SYS_EEPROM_WP));
256 #ifdef CONFIG_CMD_DISPLAY
257 #define DISPLAY_BUF_SIZE 2
258 static u8 display_buf[DISPLAY_BUF_SIZE];
259 static u8 display_putc_pos;
260 static u8 display_out_pos;
262 void display_set(int cmd) {
264 if (cmd & DISPLAY_CLEAR) {
265 display_buf[0] = display_buf[1] = 0;
268 if (cmd & DISPLAY_HOME) {
269 display_putc_pos = 0;
301 #define SYMBOL_DASH (36)
302 #define SYMBOL_UNDERLINE (37)
303 #define SYMBOL_DOT (38)
305 static u8 display_char2seg7_tbl[]=
307 SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* 0 */
308 SEG_B | SEG_C, /* 1 */
309 SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* 2 */
310 SEG_A | SEG_B | SEG_C | SEG_D | SEG_G, /* 3 */
311 SEG_B | SEG_C | SEG_F | SEG_G, /* 4 */
312 SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* 5 */
313 SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 6 */
314 SEG_A | SEG_B | SEG_C, /* 7 */
315 SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 8 */
316 SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* 9 */
317 SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* A */
318 SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* b */
319 SEG_A | SEG_D | SEG_E | SEG_F, /* C */
320 SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, /* d */
321 SEG_A | SEG_D | SEG_E | SEG_F | SEG_G, /* E */
322 SEG_A | SEG_E | SEG_F | SEG_G, /* F */
323 0, /* g - not displayed */
324 SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* H */
325 SEG_B | SEG_C, /* I */
326 0, /* J - not displayed */
327 0, /* K - not displayed */
328 SEG_D | SEG_E | SEG_F, /* L */
329 0, /* m - not displayed */
330 0, /* n - not displayed */
331 SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* O */
332 SEG_A | SEG_B | SEG_E | SEG_F | SEG_G, /* P */
333 0, /* q - not displayed */
334 0, /* r - not displayed */
335 SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* S */
336 SEG_D | SEG_E | SEG_F | SEG_G, /* t */
337 SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* U */
338 0, /* V - not displayed */
339 0, /* w - not displayed */
340 0, /* X - not displayed */
341 SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* Y */
342 0, /* Z - not displayed */
348 /* Convert char to the LED segments representation */
349 static u8 display_char2seg7(char c)
353 if (c >= '0' && c <= '9')
355 else if (c >= 'a' && c <= 'z')
357 else if (c >= 'A' && c <= 'Z')
362 c = SYMBOL_UNDERLINE;
366 c = ' '; /* display unsupported symbols as space */
369 val = display_char2seg7_tbl[(int)c];
374 int display_putc(char c)
376 if (display_putc_pos >= DISPLAY_BUF_SIZE)
379 display_buf[display_putc_pos++] = display_char2seg7(c);
380 /* one-symbol message should be steady */
381 if (display_putc_pos == 1)
382 display_buf[display_putc_pos] = display_char2seg7(c);
388 * Flush current symbol to the LED display hardware
390 static inline void display_flush(void)
392 u32 val = display_buf[display_out_pos];
394 val |= (val << 8) | (val << 16) | (val << 24);
395 out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val);
399 * Output contents of the software display buffer to the LED display every 0.5s
401 void board_show_activity(ulong timestamp)
406 if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) {
408 display_out_pos ^= 1;
415 * Empty fake function
417 void show_activity(int arg)
421 #if defined (CONFIG_SHOW_BOOT_PROGRESS)
422 static int a4m072_status2code(int status, char *buf)
426 if (((status > 0) && (status <= 8)) ||
427 ((status >= 100) && (status <= 108)) ||
428 ((status < 0) && (status >= -9)) ||
429 (status == -100) || (status == -101) ||
430 ((status <= -103) && (status >= -113))) {
432 } else if (((status >= 9) && (status <= 14)) ||
433 ((status >= 120) && (status <= 123)) ||
434 ((status >= 125) && (status <= 129)) ||
435 ((status >= -13) && (status <= -10)) ||
436 (status == -120) || (status == -122) ||
437 ((status <= -124) && (status >= -127)) ||
440 } else if (status == 15) {
442 } else if ((status <= -30) && (status >= -32)) {
444 } else if (((status <= -35) && (status >= -40)) ||
445 ((status <= -42) && (status >= -51)) ||
446 ((status <= -53) && (status >= -58)) ||
448 ((status <= -80) && (status >= -83)) ||
449 (status == -130) || (status == -140) ||
457 buf[0] = (status < 0) ? '-' : c;
463 void show_boot_progress(int status)
467 if (a4m072_status2code(status, buf) < 0)
470 display_putc(buf[0]);
471 display_putc(buf[1]);
472 display_set(DISPLAY_HOME);
473 display_out_pos = 0; /* reset output position */
475 /* we want to flush status 15 now */
476 if (status == BOOTSTAGE_ID_RUN_OS)