1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2012
4 * Wojciech Dubowik <wojciech.dubowik@neratec.com>
5 * Luka Perkov <luka@openwrt.org>
12 #include <asm/setup.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
15 #include <asm/arch/mpp.h>
16 #include <linux/delay.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 int board_early_init_f(void)
24 * default gpio configuration
25 * There are maximum 64 gpios controlled through 2 sets of registers
26 * the below configuration configures mainly initial LED status
28 mvebu_config_gpio(DS109_OE_VAL_LOW,
30 DS109_OE_LOW, DS109_OE_HIGH);
32 /* Multi-Purpose Pins Functionality configuration */
33 static const u32 kwmpp_config[] = {
34 MPP0_SPI_SCn, /* SPI Flash */
40 MPP6_SYSRST_OUTn, /* Reset signal */
42 MPP8_TW_SDA, /* I2C */
43 MPP9_TW_SCK, /* I2C */
56 MPP22_GPIO, /* HDD2 FAIL LED */
57 MPP23_GPIO, /* HDD1 FAIL LED */
65 MPP31_GPIO, /* HDD2 */
66 MPP32_GPIO, /* FAN A */
67 MPP33_GPIO, /* FAN B */
68 MPP34_GPIO, /* FAN C */
69 MPP35_GPIO, /* FAN SENSE */
86 kirkwood_mpp_conf(kwmpp_config, NULL);
92 /* address of boot parameters */
93 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
98 /* Synology reset uses UART */
100 #define SOFTWARE_SHUTDOWN 0x31
101 #define SOFTWARE_REBOOT 0x43
102 #define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
103 void reset_misc(void)
106 printf("Synology reset...");
109 b_d = ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM2,
110 CONFIG_SYS_NS16550_CLK, 9600);
111 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM2, b_d);
112 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, SOFTWARE_REBOOT);
115 /* Support old kernels */
116 void setup_board_tags(struct tag **in_params)
118 unsigned int boardId;
120 struct tag_mv_uboot *t;
123 printf("Synology board tags...");
125 t = (struct tag_mv_uboot *)¶ms->u;
127 t->uboot_version = VER_NUM;
129 boardId = SYNO_DS109_ID;
130 t->uboot_version |= boardId;
132 t->tclk = CONFIG_SYS_TCLK;
133 t->sysclk = CONFIG_SYS_TCLK*2;
136 for (i = 0; i < 4; i++) {
137 memset(t->macaddr[i], 0, sizeof(t->macaddr[i]));
141 params->hdr.tag = ATAG_MV_UBOOT;
142 params->hdr.size = tag_size(tag_mv_uboot);
143 params = tag_next(params);
147 #ifdef CONFIG_RESET_PHY_R
148 /* Configure and enable MV88E1116 PHY */
153 char *name = "egiga0";
155 if (miiphy_set_current_dev(name))
158 /* command to read PHY dev address */
159 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
160 printf("Error: 88E1116 could not read PHY dev address\n");
165 * Enable RGMII delay on Tx and Rx for CPU port
166 * Ref: sec 4.7.2 of chip datasheet
168 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
169 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
170 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
171 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
172 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
175 miiphy_reset(name, devadr);
177 printf("88E1116 Initialized on %s\n", name);
179 #endif /* CONFIG_RESET_PHY_R */