1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2012
4 * Wojciech Dubowik <wojciech.dubowik@neratec.com>
5 * Luka Perkov <luka@openwrt.org>
10 #include <asm/setup.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
13 #include <asm/arch/mpp.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 int board_early_init_f(void)
21 * default gpio configuration
22 * There are maximum 64 gpios controlled through 2 sets of registers
23 * the below configuration configures mainly initial LED status
25 mvebu_config_gpio(DS109_OE_VAL_LOW,
27 DS109_OE_LOW, DS109_OE_HIGH);
29 /* Multi-Purpose Pins Functionality configuration */
30 static const u32 kwmpp_config[] = {
31 MPP0_SPI_SCn, /* SPI Flash */
37 MPP6_SYSRST_OUTn, /* Reset signal */
39 MPP8_TW_SDA, /* I2C */
40 MPP9_TW_SCK, /* I2C */
53 MPP22_GPIO, /* HDD2 FAIL LED */
54 MPP23_GPIO, /* HDD1 FAIL LED */
62 MPP31_GPIO, /* HDD2 */
63 MPP32_GPIO, /* FAN A */
64 MPP33_GPIO, /* FAN B */
65 MPP34_GPIO, /* FAN C */
66 MPP35_GPIO, /* FAN SENSE */
83 kirkwood_mpp_conf(kwmpp_config, NULL);
89 /* address of boot parameters */
90 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
95 /* Synology reset uses UART */
97 #define SOFTWARE_SHUTDOWN 0x31
98 #define SOFTWARE_REBOOT 0x43
99 #define CONFIG_SYS_NS16550_COM2 KW_UART1_BASE
100 void reset_misc(void)
103 printf("Synology reset...");
106 b_d = ns16550_calc_divisor((NS16550_t)CONFIG_SYS_NS16550_COM2,
107 CONFIG_SYS_NS16550_CLK, 9600);
108 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM2, b_d);
109 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM2, SOFTWARE_REBOOT);
112 /* Support old kernels */
113 void setup_board_tags(struct tag **in_params)
115 unsigned int boardId;
117 struct tag_mv_uboot *t;
120 printf("Synology board tags...");
122 t = (struct tag_mv_uboot *)¶ms->u;
124 t->uboot_version = VER_NUM;
126 boardId = SYNO_DS109_ID;
127 t->uboot_version |= boardId;
129 t->tclk = CONFIG_SYS_TCLK;
130 t->sysclk = CONFIG_SYS_TCLK*2;
133 for (i = 0; i < 4; i++) {
134 memset(t->macaddr[i], 0, sizeof(t->macaddr[i]));
138 params->hdr.tag = ATAG_MV_UBOOT;
139 params->hdr.size = tag_size(tag_mv_uboot);
140 params = tag_next(params);
144 #ifdef CONFIG_RESET_PHY_R
145 /* Configure and enable MV88E1116 PHY */
150 char *name = "egiga0";
152 if (miiphy_set_current_dev(name))
155 /* command to read PHY dev address */
156 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
157 printf("Error: 88E1116 could not read PHY dev address\n");
162 * Enable RGMII delay on Tx and Rx for CPU port
163 * Ref: sec 4.7.2 of chip datasheet
165 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
166 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
167 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
168 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
169 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
172 miiphy_reset(name, devadr);
174 printf("88E1116 Initialized on %s\n", name);
176 #endif /* CONFIG_RESET_PHY_R */