3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
28 #include <asm/arch/kirkwood.h>
29 #include <asm/arch/mpp.h>
32 DECLARE_GLOBAL_DATA_PTR;
37 * default gpio configuration
38 * There are maximum 64 gpios controlled through 2 sets of registers
39 * the below configuration configures mainly initial LED status
41 kw_config_gpio(RD6281A_OE_VAL_LOW,
43 RD6281A_OE_LOW, RD6281A_OE_HIGH);
45 /* Multi-Purpose Pins Functionality configuration */
46 u32 kwmpp_config[] = {
99 kirkwood_mpp_conf(kwmpp_config);
102 * arch number of board
104 gd->bd->bi_arch_number = MACH_TYPE_RD88F6281;
106 /* adress of boot parameters */
107 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
116 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
117 gd->bd->bi_dram[i].start = kw_sdram_bar(i);
118 gd->bd->bi_dram[i].size = kw_sdram_bs(i);
123 void mv_phy_88e1116_init(char *name)
128 if (miiphy_set_current_dev(name))
131 /* command to read PHY dev address */
132 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
133 printf("Err..%s could not read PHY dev address\n",
139 * Enable RGMII delay on Tx and Rx for CPU port
140 * Ref: sec 4.7.2 of chip datasheet
142 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
143 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
144 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
145 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
146 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
149 if (miiphy_read (name, devadr, PHY_BMCR, ®) != 0) {
150 printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
153 if (miiphy_write (name, devadr, PHY_BMCR, reg | 0x8000) != 0) {
154 printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
158 printf("88E1116 Initialized on %s\n", name);
161 /* Configure and enable Switch and PHY */
164 /* configure and initialize switch */
165 struct mv88e61xx_config swcfg = {
167 .vlancfg = MV88E61XX_VLANCFG_ROUTER,
168 .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
169 .led_init = MV88E61XX_LED_INIT_EN,
170 .portstate = MV88E61XX_PORTSTT_FORWARDING,
172 .ports_enabled = 0x3f,
175 mv88e61xx_switch_initialize(&swcfg);
177 /* configure and initialize PHY */
178 mv_phy_88e1116_init("egiga1");