1 // SPDX-License-Identifier: GPL-2.0+
4 * Jason Cooper <u-boot@lakedaemon.net>
7 * Marvell Semiconductor <www.marvell.com>
8 * Written-by: Siddarth Gore <gores@marvell.com>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/soc.h>
17 #include <asm/arch/mpp.h>
18 #include "dreamplug.h"
20 DECLARE_GLOBAL_DATA_PTR;
22 int board_early_init_f(void)
25 * default gpio configuration
26 * There are maximum 64 gpios controlled through 2 sets of registers
27 * the below configuration configures mainly initial LED status
29 mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
30 DREAMPLUG_OE_VAL_HIGH,
31 DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
33 /* Multi-Purpose Pins Functionality configuration */
34 static const u32 kwmpp_config[] = {
35 MPP0_SPI_SCn, /* SPI Flash */
45 MPP10_UART0_TXD, /* Serial */
47 MPP12_SD_CLK, /* SDIO Slot */
55 MPP20_GE1_0, /* Gigabit Ethernet */
71 MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
82 MPP47_GPIO, /* Bluetooth LED */
83 MPP48_GPIO, /* Wifi LED */
84 MPP49_GPIO, /* Wifi AP LED */
87 kirkwood_mpp_conf(kwmpp_config, NULL);
93 /* adress of boot parameters */
94 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
99 #ifdef CONFIG_RESET_PHY_R
100 void mv_phy_88e1116_init(char *name)
105 if (miiphy_set_current_dev(name))
108 /* command to read PHY dev address */
109 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
110 printf("Err..%s could not read PHY dev address\n",
116 * Enable RGMII delay on Tx and Rx for CPU port
117 * Ref: sec 4.7.2 of chip datasheet
119 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
120 miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
121 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
122 miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
123 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
126 miiphy_reset(name, devadr);
128 printf("88E1116 Initialized on %s\n", name);
133 /* configure and initialize both PHY's */
134 mv_phy_88e1116_init("egiga0");
135 mv_phy_88e1116_init("egiga1");
137 #endif /* CONFIG_RESET_PHY_R */