3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * modifications for the DB64460 eval board based by Ingo.Assmus@keymile.com
27 * db64460.c - main board support/init for the Galileo Eval board.
32 #include "../include/memory.h"
33 #include "../include/pci.h"
34 #include "../include/mv_gen_reg.h"
54 /* ------------------------------------------------------------------------- */
56 /* this is the current GT register space location */
57 /* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
59 /* Unfortunately, we cant change it while we are in flash, so we initialize it
60 * to the "final" value. This means that any debug_led calls before
61 * board_early_init_f wont work right (like in cpu_init_f).
62 * See also my_remap_gt_regs below. (NTL)
65 void board_prebootm_init (void);
66 unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
67 int display_mem_map (void);
69 /* ------------------------------------------------------------------------- */
72 * This is a version of the GT register space remapping function that
73 * doesn't touch globals (meaning, it's ok to run from flash.)
75 * Unfortunately, this has the side effect that a writable
76 * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
79 void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
83 /* check and see if it's already moved */
85 /* original ppcboot 1.1.6 source
87 temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
88 if ((temp & 0xffff) == new_loc >> 20)
91 temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
92 0xffff0000) | (new_loc >> 20);
94 out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
96 while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
97 original ppcboot 1.1.6 source end */
99 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
100 if ((temp & 0xffff) == new_loc >> 16)
103 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
104 0xffff0000) | (new_loc >> 16);
106 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
108 while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
113 static void gt_pci_config (void)
116 unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
118 /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
119 * config registers by writing ones to the bus and device.
120 * We then update the Virtual register with the correct value for the bus and device.
122 if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
123 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
125 GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
127 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
128 GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
129 (stat & 0xffff0000) | CFG_PCI_IDSEL);
132 if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
133 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
134 GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
136 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
137 GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
138 (stat & 0xffff0000) | CFG_PCI_IDSEL);
142 PCI_MASTER_ENABLE (0, SELF);
143 PCI_MASTER_ENABLE (1, SELF);
145 /* Enable PCI0/1 Mem0 and IO 0 disable all others */
146 GT_REG_READ (BASE_ADDR_ENABLE, &stat);
147 stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
150 stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
151 GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
153 /* ronen- add write to pci remap registers for 64460.
154 in 64360 when writing to pci base go and overide remap automaticaly,
155 in 64460 it doesn't */
156 GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
157 GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
158 GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
160 GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
161 GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
162 GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
164 GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
165 GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
166 GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
168 GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
169 GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
170 GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
172 /* PCI interface settings */
173 /* Timeout set to retry forever */
174 GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
175 GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
177 /* ronen - enable only CS0 and Internal reg!! */
178 GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
179 GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
181 /*ronen update the pci internal registers base address.*/
183 for (stat = 0; stat <= PCI_HOST1; stat++)
184 pciWriteConfigReg (stat,
185 PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
192 /* Setup CPU interface paramaters */
193 static void gt_cpu_config (void)
195 cpu_t cpu = get_cpu_type ();
198 /* cpu configuration register */
199 tmp = GTREGREAD (CPU_CONFIGURATION);
201 /* set the SINGLE_CPU bit see MV64460 P.399 */
202 #ifndef CFG_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
203 tmp |= CPU_CONF_SINGLE_CPU;
206 tmp &= ~CPU_CONF_AACK_DELAY_2;
208 tmp |= CPU_CONF_DP_VALID;
209 tmp |= CPU_CONF_AP_VALID;
211 tmp |= CPU_CONF_PIPELINE;
213 GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
215 /* CPU master control register */
216 tmp = GTREGREAD (CPU_MASTER_CONTROL);
218 tmp |= CPU_MAST_CTL_ARB_EN;
220 if ((cpu == CPU_7400) ||
221 (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
223 tmp |= CPU_MAST_CTL_CLEAN_BLK;
224 tmp |= CPU_MAST_CTL_FLUSH_BLK;
227 /* cleanblock must be cleared for CPUs
228 * that do not support this command (603e, 750)
230 tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
231 tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
233 GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
237 * board_early_init_f.
239 * set up gal. device mappings, etc.
241 int board_early_init_f (void)
246 * set up the GT the way the kernel wants it
247 * the call to move the GT register space will obviously
248 * fail if it has already been done, but we're going to assume
249 * that if it's not at the power-on location, it's where we put
250 * it last time. (huber)
253 my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
255 /* No PCI in first release of Port To_do: enable it. */
259 /* mask all external interrupt sources */
260 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
261 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
263 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
264 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
265 /* --------------------- */
266 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
267 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
268 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
269 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
270 /* does not exist in MV6446x
271 GT_REG_WRITE(CPU_INT_0_MASK, 0);
272 GT_REG_WRITE(CPU_INT_1_MASK, 0);
273 GT_REG_WRITE(CPU_INT_2_MASK, 0);
274 GT_REG_WRITE(CPU_INT_3_MASK, 0);
275 --------------------- */
278 /* ----- DEVICE BUS SETTINGS ------ */
285 * 3 - Flash checked 32Bit Intel Strata
286 * boot - BootCS checked 8Bit 29LV040B
294 * the dual 7450 module requires burst access to the boot
295 * device, so the serial rom copies the boot device to the
296 * on-board sram on the eval board, and updates the correct
297 * registers to boot from the sram. (device0)
299 if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
302 memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
304 memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
305 memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
306 memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
309 /* configure device timing */
310 #ifdef CFG_DEV0_PAR /* set port parameters for SRAM device module access */
312 GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
315 #ifdef CFG_DEV1_PAR /* set port parameters for RTC device module access */
316 GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
318 #ifdef CFG_DEV2_PAR /* set port parameters for DUART device module access */
319 GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
322 #ifdef CFG_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
323 /* detect if we are booting from the 32 bit flash */
324 if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
325 /* 32 bit boot flash */
326 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
327 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
330 /* 8 bit boot flash */
331 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
332 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
335 /* 8 bit boot flash only */
336 /* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
343 GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
344 GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
345 GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
346 GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
348 GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
356 /* various things to do after relocation */
371 /* disable the dcache and MMU */
377 void after_reloc (ulong dest_addr, gd_t * gd)
379 /* check to see if we booted from the sram. If so, move things
380 * back to the way they should be. (we're running from main
381 * memory at this point now */
382 if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
383 memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
384 memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
387 /* now, jump to the main ppcboot board init code */
388 board_init_r (gd, dest_addr);
392 /* ------------------------------------------------------------------------- */
395 * Check Board Identity:
397 * right now, assume borad type. (there is just one...after all)
400 int checkboard (void)
404 printf ("BOARD: %s\n", CFG_BOARD_NAME);
408 /* utility functions */
409 void debug_led (int led, int mode)
411 volatile int *addr = 0;
417 addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
422 addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
427 addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
431 } else if (mode == 0) {
434 addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
439 addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
444 addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
453 int display_mem_map (void)
456 unsigned int base, size, width;
459 printf ("SD (DDR) RAM\n");
460 for (i = 0; i <= BANK3; i++) {
461 base = memoryGetBankBaseAddress (i);
462 size = memoryGetBankSize (i);
464 printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
465 i, base, size >> 20);
469 /* CPU's PCI windows */
470 for (i = 0; i <= PCI_HOST1; i++) {
471 printf ("\nCPU's PCI %d windows\n", i);
472 base = pciGetSpaceBase (i, PCI_IO);
473 size = pciGetSpaceSize (i, PCI_IO);
474 printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
479 /*ronen currently only first PCI MEM is used 3 */ ;
481 base = pciGetSpaceBase (i, j);
482 size = pciGetSpaceSize (i, j);
483 printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
488 printf ("\nDEVICES\n");
489 for (i = 0; i <= DEVICE3; i++) {
490 base = memoryGetDeviceBaseAddress (i);
491 size = memoryGetDeviceSize (i);
492 width = memoryGetDeviceWidth (i) * 8;
493 printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
495 printf ("\t- EXT SRAM (actual - 1M)\n");
497 printf ("\t- RTC\n");
499 printf ("\t- UART\n");
501 printf ("\t- LARGE FLASH\n");
505 base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
506 size = memoryGetDeviceSize (BOOT_DEVICE);
507 width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
508 printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n",
509 base, size >> 20, width);
513 /* DRAM check routines copied from gw8260 */
515 #if defined (CFG_DRAM_TEST)
517 /*********************************************************************/
518 /* NAME: move64() - moves a double word (64-bit) */
521 /* this function performs a double word move from the data at */
522 /* the source pointer to the location at the destination pointer. */
525 /* unsigned long long *src - pointer to data to move */
528 /* unsigned long long *dest - pointer to locate to move data */
533 /* RESTRICTIONS/LIMITATIONS: */
534 /* May cloober fr0. */
536 /*********************************************************************/
537 static void move64 (unsigned long long *src, unsigned long long *dest)
539 asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
540 "stfd 0, 0(4)" /* *dest = fpr0 */
541 : : : "fr0"); /* Clobbers fr0 */
546 #if defined (CFG_DRAM_TEST_DATA)
548 unsigned long long pattern[] = {
549 0xaaaaaaaaaaaaaaaaULL,
550 0xccccccccccccccccULL,
551 0xf0f0f0f0f0f0f0f0ULL,
552 0xff00ff00ff00ff00ULL,
553 0xffff0000ffff0000ULL,
554 0xffffffff00000000ULL,
555 0x00000000ffffffffULL,
556 0x0000ffff0000ffffULL,
557 0x00ff00ff00ff00ffULL,
558 0x0f0f0f0f0f0f0f0fULL,
559 0x3333333333333333ULL,
560 0x5555555555555555ULL,
563 /*********************************************************************/
564 /* NAME: mem_test_data() - test data lines for shorts and opens */
567 /* Tests data lines for shorts and opens by forcing adjacent data */
568 /* to opposite states. Because the data lines could be routed in */
569 /* an arbitrary manner the must ensure test patterns ensure that */
570 /* every case is tested. By using the following series of binary */
571 /* patterns every combination of adjacent bits is test regardless */
574 /* ...101010101010101010101010 */
575 /* ...110011001100110011001100 */
576 /* ...111100001111000011110000 */
577 /* ...111111110000000011111111 */
579 /* Carrying this out, gives us six hex patterns as follows: */
581 /* 0xaaaaaaaaaaaaaaaa */
582 /* 0xcccccccccccccccc */
583 /* 0xf0f0f0f0f0f0f0f0 */
584 /* 0xff00ff00ff00ff00 */
585 /* 0xffff0000ffff0000 */
586 /* 0xffffffff00000000 */
588 /* The number test patterns will always be given by: */
590 /* log(base 2)(number data bits) = log2 (64) = 6 */
592 /* To test for short and opens to other signals on our boards. we */
594 /* test with the 1's complemnt of the paterns as well. */
597 /* Displays failing test pattern */
600 /* 0 - Passed test */
601 /* 1 - Failed test */
603 /* RESTRICTIONS/LIMITATIONS: */
604 /* Assumes only one one SDRAM bank */
606 /*********************************************************************/
607 int mem_test_data (void)
609 unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
610 unsigned long long temp64 = 0;
611 int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
615 for (i = 0; i < num_patterns; i++) {
616 move64 (&(pattern[i]), pmem);
617 move64 (pmem, &temp64);
619 /* hi = (temp64>>32) & 0xffffffff; */
620 /* lo = temp64 & 0xffffffff; */
621 /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
623 hi = (pattern[i] >> 32) & 0xffffffff;
624 lo = pattern[i] & 0xffffffff;
625 /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
627 if (temp64 != pattern[i]) {
628 printf ("\n Data Test Failed, pattern 0x%08x%08x",
636 #endif /* CFG_DRAM_TEST_DATA */
638 #if defined (CFG_DRAM_TEST_ADDRESS)
639 /*********************************************************************/
640 /* NAME: mem_test_address() - test address lines */
643 /* This function performs a test to verify that each word im */
644 /* memory is uniquly addressable. The test sequence is as follows: */
646 /* 1) write the address of each word to each word. */
647 /* 2) verify that each location equals its address */
650 /* Displays failing test pattern and address */
653 /* 0 - Passed test */
654 /* 1 - Failed test */
656 /* RESTRICTIONS/LIMITATIONS: */
659 /*********************************************************************/
660 int mem_test_address (void)
662 volatile unsigned int *pmem =
663 (volatile unsigned int *) CFG_MEMTEST_START;
664 const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
667 /* write address to each location */
668 for (i = 0; i < size; i++) {
672 /* verify each loaction */
673 for (i = 0; i < size; i++) {
675 printf ("\n Address Test Failed at 0x%x", i);
681 #endif /* CFG_DRAM_TEST_ADDRESS */
683 #if defined (CFG_DRAM_TEST_WALK)
684 /*********************************************************************/
685 /* NAME: mem_march() - memory march */
688 /* Marches up through memory. At each location verifies rmask if */
689 /* read = 1. At each location write wmask if write = 1. Displays */
690 /* failing address and pattern. */
693 /* volatile unsigned long long * base - start address of test */
694 /* unsigned int size - number of dwords(64-bit) to test */
695 /* unsigned long long rmask - read verify mask */
696 /* unsigned long long wmask - wrtie verify mask */
697 /* short read - verifies rmask if read = 1 */
698 /* short write - writes wmask if write = 1 */
701 /* Displays failing test pattern and address */
704 /* 0 - Passed test */
705 /* 1 - Failed test */
707 /* RESTRICTIONS/LIMITATIONS: */
710 /*********************************************************************/
711 int mem_march (volatile unsigned long long *base,
713 unsigned long long rmask,
714 unsigned long long wmask, short read, short write)
717 unsigned long long temp = 0;
718 unsigned int hitemp, lotemp, himask, lomask;
720 for (i = 0; i < size; i++) {
722 /* temp = base[i]; */
723 move64 ((unsigned long long *) &(base[i]), &temp);
725 hitemp = (temp >> 32) & 0xffffffff;
726 lotemp = temp & 0xffffffff;
727 himask = (rmask >> 32) & 0xffffffff;
728 lomask = rmask & 0xffffffff;
730 printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
735 /* base[i] = wmask; */
736 move64 (&wmask, (unsigned long long *) &(base[i]));
741 #endif /* CFG_DRAM_TEST_WALK */
743 /*********************************************************************/
744 /* NAME: mem_test_walk() - a simple walking ones test */
747 /* Performs a walking ones through entire physical memory. The */
748 /* test uses as series of memory marches, mem_march(), to verify */
749 /* and write the test patterns to memory. The test sequence is as */
751 /* 1) march writing 0000...0001 */
752 /* 2) march verifying 0000...0001 , writing 0000...0010 */
753 /* 3) repeat step 2 shifting masks left 1 bit each time unitl */
754 /* the write mask equals 1000...0000 */
755 /* 4) march verifying 1000...0000 */
756 /* The test fails if any of the memory marches return a failure. */
759 /* Displays which pass on the memory test is executing */
762 /* 0 - Passed test */
763 /* 1 - Failed test */
765 /* RESTRICTIONS/LIMITATIONS: */
768 /*********************************************************************/
769 int mem_test_walk (void)
771 unsigned long long mask;
772 volatile unsigned long long *pmem =
773 (volatile unsigned long long *) CFG_MEMTEST_START;
774 const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
780 printf ("Initial Pass");
781 mem_march (pmem, size, 0x0, 0x1, 0, 1);
783 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
786 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
788 for (i = 0; i < 63; i++) {
789 printf ("Pass %2d", i + 2);
790 if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
791 /*printf("mask: 0x%x, pass: %d, ", mask, i); */
795 printf ("\b\b\b\b\b\b\b");
798 printf ("Last Pass");
799 if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
800 /* printf("mask: 0x%x", mask); */
803 printf ("\b\b\b\b\b\b\b\b\b");
805 printf ("\b\b\b\b\b\b\b\b\b");
810 /*********************************************************************/
811 /* NAME: testdram() - calls any enabled memory tests */
814 /* Runs memory tests if the environment test variables are set to */
818 /* testdramdata - If set to 'y', data test is run. */
819 /* testdramaddress - If set to 'y', address test is run. */
820 /* testdramwalk - If set to 'y', walking ones test is run */
826 /* 0 - Passed test */
827 /* 1 - Failed test */
829 /* RESTRICTIONS/LIMITATIONS: */
832 /*********************************************************************/
836 int rundata, runaddress, runwalk;
838 s = getenv ("testdramdata");
839 rundata = (s && (*s == 'y')) ? 1 : 0;
840 s = getenv ("testdramaddress");
841 runaddress = (s && (*s == 'y')) ? 1 : 0;
842 s = getenv ("testdramwalk");
843 runwalk = (s && (*s == 'y')) ? 1 : 0;
846 /* runaddress = 0; */
849 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
850 printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
852 #ifdef CFG_DRAM_TEST_DATA
854 printf ("Test DATA ... ");
855 if (mem_test_data () == 1) {
856 printf ("failed \n");
862 #ifdef CFG_DRAM_TEST_ADDRESS
863 if (runaddress == 1) {
864 printf ("Test ADDRESS ... ");
865 if (mem_test_address () == 1) {
866 printf ("failed \n");
872 #ifdef CFG_DRAM_TEST_WALK
874 printf ("Test WALKING ONEs ... ");
875 if (mem_test_walk () == 1) {
876 printf ("failed \n");
882 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
888 #endif /* CFG_DRAM_TEST */
890 /* ronen - the below functions are used by the bootm function */
891 /* - we map the base register to fbe00000 (same mapping as in the LSP) */
892 /* - we turn off the RX gig dmas - to prevent the dma from overunning */
893 /* the kernel data areas. */
894 /* - we diable and invalidate the icache and dcache. */
895 void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
899 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
900 if ((temp & 0xffff) == new_loc >> 16)
903 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
904 0xffff0000) | (new_loc >> 16);
906 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
908 while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
910 (INTERNAL_SPACE_DECODE)))))
915 void board_prebootm_init ()
918 /* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
919 GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
921 /* Stop GigE Rx DMA engines */
922 GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
923 GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
924 GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00);
926 /* Relocate MV64460 internal regs */
927 my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);