3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
7 /* PCI.c - PCI functions */
13 #include "../include/pci.h"
16 #undef IDE_SET_NATIVE_MODE
17 static unsigned int local_buses[] = { 0, 0 };
19 static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
20 {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
21 {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
26 static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
27 static void gt_pci_bus_mode_display (PCI_HOST host)
32 mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
35 printf ("PCI %d bus mode: Conventional PCI\n", host);
38 printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
41 printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
44 printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
47 printf ("Unknown BUS %d\n", mode);
52 static const unsigned int pci_p2p_configuration_reg[] = {
53 PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
56 static const unsigned int pci_configuration_address[] = {
57 PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
60 static const unsigned int pci_configuration_data[] = {
61 PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
62 PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
65 static const unsigned int pci_error_cause_reg[] = {
66 PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
69 static const unsigned int pci_arbiter_control[] = {
70 PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
73 static const unsigned int pci_address_space_en[] = {
74 PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
77 static const unsigned int pci_snoop_control_base_0_low[] = {
78 PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
80 static const unsigned int pci_snoop_control_top_0[] = {
81 PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
84 static const unsigned int pci_access_control_base_0_low[] = {
85 PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
87 static const unsigned int pci_access_control_top_0[] = {
88 PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
91 static const unsigned int pci_scs_bank_size[2][4] = {
92 {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
93 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
94 {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
95 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
98 static const unsigned int pci_p2p_configuration[] = {
99 PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
103 /********************************************************************
104 * pciWriteConfigReg - Write to a PCI configuration register
105 * - Make sure the GT is configured as a master before writing
106 * to another device on the PCI.
107 * - The function takes care of Big/Little endian conversion.
110 * Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
111 * (or any other PCI device spec)
112 * pciDevNum: The device number needs to be addressed.
114 * Configuration Address 0xCF8:
116 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
117 * |congif|Reserved| Bus |Device|Function|Register|00|
118 * |Enable| |Number|Number| Number | Number | | <=field Name
120 *********************************************************************/
121 void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
122 unsigned int pciDevNum, unsigned int data)
124 volatile unsigned int DataForAddrReg;
125 unsigned int functionNum;
126 unsigned int busNum = 0;
129 if (pciDevNum > 32) /* illegal device Number */
131 if (pciDevNum == SELF) { /* configure our configuration space. */
133 (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
135 busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
138 functionNum = regOffset & 0x00000700;
139 pciDevNum = pciDevNum << 11;
140 regOffset = regOffset & 0xfc;
142 (regOffset | pciDevNum | functionNum | busNum) | BIT31;
143 GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
144 GT_REG_READ (pci_configuration_address[host], &addr);
145 if (addr != DataForAddrReg)
147 GT_REG_WRITE (pci_configuration_data[host], data);
150 /********************************************************************
151 * pciReadConfigReg - Read from a PCI0 configuration register
152 * - Make sure the GT is configured as a master before reading
153 * from another device on the PCI.
154 * - The function takes care of Big/Little endian conversion.
155 * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
157 * pciDevNum: The device number needs to be addressed.
158 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
159 * cause register to make sure the data is valid
161 * Configuration Address 0xCF8:
163 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
164 * |congif|Reserved| Bus |Device|Function|Register|00|
165 * |Enable| |Number|Number| Number | Number | | <=field Name
167 *********************************************************************/
168 unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
169 unsigned int pciDevNum)
171 volatile unsigned int DataForAddrReg;
173 unsigned int functionNum;
174 unsigned int busNum = 0;
176 if (pciDevNum > 32) /* illegal device Number */
178 if (pciDevNum == SELF) { /* configure our configuration space. */
180 (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
182 busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
185 functionNum = regOffset & 0x00000700;
186 pciDevNum = pciDevNum << 11;
187 regOffset = regOffset & 0xfc;
189 (regOffset | pciDevNum | functionNum | busNum) | BIT31;
190 GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
191 GT_REG_READ (pci_configuration_address[host], &data);
192 if (data != DataForAddrReg)
194 GT_REG_READ (pci_configuration_data[host], &data);
198 /********************************************************************
199 * pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
200 * the agent is placed on another Bus. For more
201 * information read P2P in the PCI spec.
203 * Inputs: unsigned int regOffset - The register offset as it apears in the
204 * GT spec (or any other PCI device spec).
205 * unsigned int pciDevNum - The device number needs to be addressed.
206 * unsigned int busNum - On which bus does the Target agent connect
208 * unsigned int data - data to be written.
210 * Configuration Address 0xCF8:
212 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
213 * |congif|Reserved| Bus |Device|Function|Register|01|
214 * |Enable| |Number|Number| Number | Number | | <=field Name
216 * The configuration Address is configure as type-I (bits[1:0] = '01') due to
217 * PCI spec referring to P2P.
219 *********************************************************************/
220 void pciOverBridgeWriteConfigReg (PCI_HOST host,
221 unsigned int regOffset,
222 unsigned int pciDevNum,
223 unsigned int busNum, unsigned int data)
225 unsigned int DataForReg;
226 unsigned int functionNum;
228 functionNum = regOffset & 0x00000700;
229 pciDevNum = pciDevNum << 11;
230 regOffset = regOffset & 0xff;
231 busNum = busNum << 16;
232 if (pciDevNum == SELF) { /* This board */
233 DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
235 DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
238 GT_REG_WRITE (pci_configuration_address[host], DataForReg);
239 GT_REG_WRITE (pci_configuration_data[host], data);
243 /********************************************************************
244 * pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
245 * the agent target locate on another PCI bus.
246 * - Make sure the GT is configured as a master
247 * before reading from another device on the PCI.
248 * - The function takes care of Big/Little endian
250 * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
251 * spec). (configuration register offset.)
252 * pciDevNum: The device number needs to be addressed.
253 * busNum: the Bus number where the agent is place.
254 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
255 * cause register to make sure the data is valid
257 * Configuration Address 0xCF8:
259 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
260 * |congif|Reserved| Bus |Device|Function|Register|01|
261 * |Enable| |Number|Number| Number | Number | | <=field Name
263 *********************************************************************/
264 unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
265 unsigned int regOffset,
266 unsigned int pciDevNum,
269 unsigned int DataForReg;
271 unsigned int functionNum;
273 functionNum = regOffset & 0x00000700;
274 pciDevNum = pciDevNum << 11;
275 regOffset = regOffset & 0xff;
276 busNum = busNum << 16;
277 if (pciDevNum == SELF) { /* This board */
278 DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
279 } else { /* agent on another bus */
281 DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
284 GT_REG_WRITE (pci_configuration_address[host], DataForReg);
285 GT_REG_READ (pci_configuration_data[host], &data);
290 /********************************************************************
291 * pciGetRegOffset - Gets the register offset for this region config.
293 * INPUT: Bus, Region - The bus and region we ask for its base address.
295 * RETURNS: PCI register base address
296 *********************************************************************/
297 static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
303 return PCI_0I_O_LOW_DECODE_ADDRESS;
305 return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
307 return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
309 return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
311 return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
316 return PCI_1I_O_LOW_DECODE_ADDRESS;
318 return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
320 return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
322 return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
324 return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
327 return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
330 static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
336 return PCI_0I_O_ADDRESS_REMAP;
338 return PCI_0MEMORY0_ADDRESS_REMAP;
340 return PCI_0MEMORY1_ADDRESS_REMAP;
342 return PCI_0MEMORY2_ADDRESS_REMAP;
344 return PCI_0MEMORY3_ADDRESS_REMAP;
349 return PCI_1I_O_ADDRESS_REMAP;
351 return PCI_1MEMORY0_ADDRESS_REMAP;
353 return PCI_1MEMORY1_ADDRESS_REMAP;
355 return PCI_1MEMORY2_ADDRESS_REMAP;
357 return PCI_1MEMORY3_ADDRESS_REMAP;
360 return PCI_0MEMORY0_ADDRESS_REMAP;
363 /********************************************************************
364 * pciGetBaseAddress - Gets the base address of a PCI.
365 * - If the PCI size is 0 then this base address has no meaning!!!
368 * INPUT: Bus, Region - The bus and region we ask for its base address.
370 * RETURNS: PCI base address.
371 *********************************************************************/
372 unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
374 unsigned int regBase;
376 unsigned int regOffset = pciGetRegOffset (host, region);
378 GT_REG_READ (regOffset, ®Base);
379 GT_REG_READ (regOffset + 8, ®End);
381 if (regEnd <= regBase)
382 return 0xffffffff; /* ERROR !!! */
384 regBase = regBase << 16;
388 bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
389 unsigned int bankBase, unsigned int bankLength)
391 unsigned int low = 0xfff;
392 unsigned int high = 0x0;
393 unsigned int regOffset = pciGetRegOffset (host, region);
394 unsigned int remapOffset = pciGetRemapOffset (host, region);
396 if (bankLength != 0) {
397 low = (bankBase >> 16) & 0xffff;
398 high = ((bankBase + bankLength) >> 16) - 1;
401 GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
402 GT_REG_WRITE (regOffset + 8, high);
404 if (bankLength != 0) { /* must do AFTER writing maps */
405 GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only.
406 dont support upper 32
412 unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
415 unsigned int regOffset = pciGetRegOffset (host, region);
417 GT_REG_READ (regOffset, &low);
418 return (low & 0xffff) << 16;
421 unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
423 unsigned int low, high;
424 unsigned int regOffset = pciGetRegOffset (host, region);
426 GT_REG_READ (regOffset, &low);
427 GT_REG_READ (regOffset + 8, &high);
428 return ((high & 0xffff) + 1) << 16;
432 /* ronen - 7/Dec/03*/
433 /********************************************************************
434 * gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
435 * Inputs: one of the PCI BAR
436 *********************************************************************/
437 void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
439 RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
442 void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
444 SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
447 /********************************************************************
448 * pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
450 * Inputs: base and size of PCI SCS
451 *********************************************************************/
452 void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
453 unsigned int pciDramBase, unsigned int pciDramSize)
455 /*ronen different function for 3rd bank. */
456 unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
458 pciDramBase = pciDramBase & 0xfffff000;
459 pciDramBase = pciDramBase | (pciReadConfigReg (host,
460 PCI_SCS_0_BASE_ADDRESS
463 pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
465 if (pciDramSize == 0)
467 GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
468 gtPciEnableInternalBAR (host, bank);
471 /********************************************************************
472 * pciSetRegionFeatures - This function modifys one of the 8 regions with
473 * feature bits given as an input.
474 * - Be advised to check the spec before modifying them.
475 * Inputs: PCI_PROTECT_REGION region - one of the eight regions.
476 * unsigned int features - See file: pci.h there are defintion for those
478 * unsigned int baseAddress - The region base Address.
479 * unsigned int topAddress - The region top Address.
480 * Returns: false if one of the parameters is erroneous true otherwise.
481 *********************************************************************/
482 bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
483 unsigned int features, unsigned int baseAddress,
484 unsigned int regionLength)
486 unsigned int accessLow;
487 unsigned int accessHigh;
488 unsigned int accessTop = baseAddress + regionLength;
490 if (regionLength == 0) { /* close the region. */
491 pciDisableAccessRegion (host, region);
494 /* base Address is store is bits [11:0] */
495 accessLow = (baseAddress & 0xfff00000) >> 20;
496 /* All the features are update according to the defines in pci.h (to be on
497 the safe side we disable bits: [11:0] */
498 accessLow = accessLow | (features & 0xfffff000);
499 /* write to the Low Access Region register */
500 GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
503 accessHigh = (accessTop & 0xfff00000) >> 20;
505 /* write to the High Access Region register */
506 GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
511 /********************************************************************
512 * pciDisableAccessRegion - Disable The given Region by writing MAX size
513 * to its low Address and MIN size to its high Address.
515 * Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
517 *********************************************************************/
518 void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
520 /* writing back the registers default values. */
521 GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
523 GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
526 /********************************************************************
527 * pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
531 *********************************************************************/
532 bool pciArbiterEnable (PCI_HOST host)
534 unsigned int regData;
536 GT_REG_READ (pci_arbiter_control[host], ®Data);
537 GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
541 /********************************************************************
542 * pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
546 *********************************************************************/
547 bool pciArbiterDisable (PCI_HOST host)
549 unsigned int regData;
551 GT_REG_READ (pci_arbiter_control[host], ®Data);
552 GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
556 /********************************************************************
557 * pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
559 * Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
560 * PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
561 * PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
562 * PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
563 * PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
564 * PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
565 * PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
567 *********************************************************************/
568 bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
569 PCI_AGENT_PRIO externalAgent0,
570 PCI_AGENT_PRIO externalAgent1,
571 PCI_AGENT_PRIO externalAgent2,
572 PCI_AGENT_PRIO externalAgent3,
573 PCI_AGENT_PRIO externalAgent4,
574 PCI_AGENT_PRIO externalAgent5)
576 unsigned int regData;
577 unsigned int writeData;
579 GT_REG_READ (pci_arbiter_control[host], ®Data);
580 writeData = (internalAgent << 7) + (externalAgent0 << 8) +
581 (externalAgent1 << 9) + (externalAgent2 << 10) +
582 (externalAgent3 << 11) + (externalAgent4 << 12) +
583 (externalAgent5 << 13);
584 regData = (regData & 0xffffc07f) | writeData;
585 GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
589 /********************************************************************
590 * pciParkingDisable - Park on last option disable, with this function you can
591 * disable the park on last mechanism for each agent.
592 * disabling this option for all agents results parking
593 * on the internal master.
595 * Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
596 * PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
597 * PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
598 * PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
599 * PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
600 * PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
601 * PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
603 *********************************************************************/
604 bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
605 PCI_AGENT_PARK externalAgent0,
606 PCI_AGENT_PARK externalAgent1,
607 PCI_AGENT_PARK externalAgent2,
608 PCI_AGENT_PARK externalAgent3,
609 PCI_AGENT_PARK externalAgent4,
610 PCI_AGENT_PARK externalAgent5)
612 unsigned int regData;
613 unsigned int writeData;
615 GT_REG_READ (pci_arbiter_control[host], ®Data);
616 writeData = (internalAgent << 14) + (externalAgent0 << 15) +
617 (externalAgent1 << 16) + (externalAgent2 << 17) +
618 (externalAgent3 << 18) + (externalAgent4 << 19) +
619 (externalAgent5 << 20);
620 regData = (regData & ~(0x7f << 14)) | writeData;
621 GT_REG_WRITE (pci_arbiter_control[host], regData);
625 /********************************************************************
626 * pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
627 * respond to grant assertion within a window specified in
628 * the input value: 'brokenValue'.
630 * Inputs: unsigned char brokenValue - A value which limits the Master to hold the
631 * grant without asserting frame.
632 * Returns: Error for illegal broken value otherwise true.
633 *********************************************************************/
634 bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
637 unsigned int regData;
639 if (brokenValue > 0xf)
640 return false; /* brokenValue must be 4 bit */
641 data = brokenValue << 3;
642 GT_REG_READ (pci_arbiter_control[host], ®Data);
643 regData = (regData & 0xffffff87) | data;
644 GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
648 /********************************************************************
649 * pciDisableBrokenAgentDetection - This function disable the Broken agent
650 * Detection mechanism.
651 * NOTE: This operation may cause a dead lock on the
656 *********************************************************************/
657 bool pciDisableBrokenAgentDetection (PCI_HOST host)
659 unsigned int regData;
661 GT_REG_READ (pci_arbiter_control[host], ®Data);
662 regData = regData & 0xfffffffd;
663 GT_REG_WRITE (pci_arbiter_control[host], regData);
667 /********************************************************************
668 * pciP2PConfig - This function set the PCI_n P2P configurate.
669 * For more information on the P2P read PCI spec.
671 * Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
673 * unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
675 * unsigned int busNum - The CPI bus number to which the PCI interface
677 * unsigned int devNum - The PCI interface's device number.
680 *********************************************************************/
681 bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
682 unsigned int SecondBusHigh,
683 unsigned int busNum, unsigned int devNum)
685 unsigned int regData;
687 regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
688 ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
689 GT_REG_WRITE (pci_p2p_configuration[host], regData);
693 /********************************************************************
694 * pciSetRegionSnoopMode - This function modifys one of the 4 regions which
695 * supports Cache Coherency in the PCI_n interface.
696 * Inputs: region - One of the four regions.
697 * snoopType - There is four optional Types:
699 * 2. Snoop to WT region.
700 * 3. Snoop to WB region.
701 * 4. Snoop & Invalidate to WB region.
702 * baseAddress - Base Address of this region.
703 * regionLength - Region length.
704 * Returns: false if one of the parameters is wrong otherwise return true.
705 *********************************************************************/
706 bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
707 PCI_SNOOP_TYPE snoopType,
708 unsigned int baseAddress,
709 unsigned int regionLength)
711 unsigned int snoopXbaseAddress;
712 unsigned int snoopXtopAddress;
714 unsigned int snoopHigh = baseAddress + regionLength;
716 if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
719 pci_snoop_control_base_0_low[host] + 0x10 * region;
720 snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
721 if (regionLength == 0) { /* closing the region */
722 GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
723 GT_REG_WRITE (snoopXtopAddress, 0);
726 baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
727 data = (baseAddress >> 20) | snoopType << 12;
728 GT_REG_WRITE (snoopXbaseAddress, data);
729 snoopHigh = (snoopHigh & 0xfff00000) >> 20;
730 GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
734 static int gt_read_config_dword (struct pci_controller *hose,
735 pci_dev_t dev, int offset, u32 * value)
737 int bus = PCI_BUS (dev);
739 if ((bus == local_buses[0]) || (bus == local_buses[1])) {
740 *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
743 *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
751 static int gt_write_config_dword (struct pci_controller *hose,
752 pci_dev_t dev, int offset, u32 value)
754 int bus = PCI_BUS (dev);
756 if ((bus == local_buses[0]) || (bus == local_buses[1])) {
757 pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
758 PCI_DEV (dev), value);
760 pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
761 offset, PCI_DEV (dev), bus,
768 static void gt_setup_ide (struct pci_controller *hose,
769 pci_dev_t dev, struct pci_config_table *entry)
771 static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
772 u32 bar_response, bar_value;
775 for (bar = 0; bar < 6; bar++) {
776 /*ronen different function for 3rd bank. */
777 unsigned int offset =
778 (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
780 pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
782 pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
785 pciauto_region_allocate (bar_response &
786 PCI_BASE_ADDRESS_SPACE_IO ? hose->
787 pci_io : hose->pci_mem, ide_bar[bar],
790 pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
796 /* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
797 /* and is curently not called *. */
799 static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
801 unsigned char pin, irq;
803 pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
805 if (pin == 1) { /* only allow INT A */
806 irq = pci_irq_swizzle[(PCI_HOST) hose->
807 cfg_addr][PCI_DEV (dev)];
809 pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
814 struct pci_config_table gt_config_table[] = {
815 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
816 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
821 struct pci_controller pci0_hose = {
822 /* fixup_irq: gt_fixup_irq, */
823 config_table:gt_config_table,
826 struct pci_controller pci1_hose = {
827 /* fixup_irq: gt_fixup_irq, */
828 config_table:gt_config_table,
831 void pci_init_board (void)
833 unsigned int command;
836 gt_pci_bus_mode_display (PCI_HOST0);
839 pci0_hose.first_busno = 0;
840 pci0_hose.last_busno = 0xff;
841 local_buses[0] = pci0_hose.first_busno;
843 /* PCI memory space */
844 pci_set_region (pci0_hose.regions + 0,
845 CONFIG_SYS_PCI0_0_MEM_SPACE,
846 CONFIG_SYS_PCI0_0_MEM_SPACE,
847 CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
850 pci_set_region (pci0_hose.regions + 1,
851 CONFIG_SYS_PCI0_IO_SPACE_PCI,
852 CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
854 pci_set_ops (&pci0_hose,
855 pci_hose_read_config_byte_via_dword,
856 pci_hose_read_config_word_via_dword,
857 gt_read_config_dword,
858 pci_hose_write_config_byte_via_dword,
859 pci_hose_write_config_word_via_dword,
860 gt_write_config_dword);
861 pci0_hose.region_count = 2;
863 pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
865 pci_register_hose (&pci0_hose);
866 pciArbiterEnable (PCI_HOST0);
867 pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
868 command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
869 command |= PCI_COMMAND_MASTER;
870 pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
871 command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
872 command |= PCI_COMMAND_MEMORY;
873 pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
875 pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
878 gt_pci_bus_mode_display (PCI_HOST1);
880 pci1_hose.first_busno = pci0_hose.last_busno + 1;
881 pci1_hose.last_busno = 0xff;
882 pci1_hose.current_busno = pci1_hose.first_busno;
883 local_buses[1] = pci1_hose.first_busno;
885 /* PCI memory space */
886 pci_set_region (pci1_hose.regions + 0,
887 CONFIG_SYS_PCI1_0_MEM_SPACE,
888 CONFIG_SYS_PCI1_0_MEM_SPACE,
889 CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
892 pci_set_region (pci1_hose.regions + 1,
893 CONFIG_SYS_PCI1_IO_SPACE_PCI,
894 CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
896 pci_set_ops (&pci1_hose,
897 pci_hose_read_config_byte_via_dword,
898 pci_hose_read_config_word_via_dword,
899 gt_read_config_dword,
900 pci_hose_write_config_byte_via_dword,
901 pci_hose_write_config_word_via_dword,
902 gt_write_config_dword);
904 pci1_hose.region_count = 2;
906 pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
908 pci_register_hose (&pci1_hose);
910 pciArbiterEnable (PCI_HOST1);
911 pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
913 command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
914 command |= PCI_COMMAND_MASTER;
915 pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
917 pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
919 command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
920 command |= PCI_COMMAND_MEMORY;
921 pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);