3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
27 * db64360.c - main board support/init for the Galileo Eval board.
32 #include "../include/memory.h"
33 #include "../include/pci.h"
34 #include "../include/mv_gen_reg.h"
37 #include <linux/compiler.h>
56 /* ------------------------------------------------------------------------- */
58 /* this is the current GT register space location */
59 /* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
61 /* Unfortunately, we cant change it while we are in flash, so we initialize it
62 * to the "final" value. This means that any debug_led calls before
63 * board_early_init_f wont work right (like in cpu_init_f).
64 * See also my_remap_gt_regs below. (NTL)
67 void board_prebootm_init (void);
68 unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
69 int display_mem_map (void);
71 /* ------------------------------------------------------------------------- */
74 * This is a version of the GT register space remapping function that
75 * doesn't touch globals (meaning, it's ok to run from flash.)
77 * Unfortunately, this has the side effect that a writable
78 * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
81 void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
85 /* check and see if it's already moved */
87 /* original ppcboot 1.1.6 source
89 temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
90 if ((temp & 0xffff) == new_loc >> 20)
93 temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
94 0xffff0000) | (new_loc >> 20);
96 out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
98 while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
99 original ppcboot 1.1.6 source end */
101 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
102 if ((temp & 0xffff) == new_loc >> 16)
105 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
106 0xffff0000) | (new_loc >> 16);
108 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
110 while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
115 static void gt_pci_config (void)
118 unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
120 /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
121 * config registers by writing ones to the bus and device.
122 * We then update the Virtual register with the correct value for the bus and device.
124 if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
125 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
127 GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
129 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
130 GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
131 (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
134 if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) { /*if PCI-X */
135 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
136 GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
138 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
139 GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
140 (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
144 PCI_MASTER_ENABLE (0, SELF);
145 PCI_MASTER_ENABLE (1, SELF);
147 /* Enable PCI0/1 Mem0 and IO 0 disable all others */
148 GT_REG_READ (BASE_ADDR_ENABLE, &stat);
149 stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
152 stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
153 GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
155 /* ronen- add write to pci remap registers for 64460.
156 in 64360 when writing to pci base go and overide remap automaticaly,
157 in 64460 it doesn't */
158 GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
159 GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
160 GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
162 GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
163 GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
164 GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
166 GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
167 GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
168 GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
170 GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
171 GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
172 GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
174 /* PCI interface settings */
175 /* Timeout set to retry forever */
176 GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
177 GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
179 /* ronen - enable only CS0 and Internal reg!! */
180 GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
181 GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
183 /*ronen update the pci internal registers base address.*/
185 for (stat = 0; stat <= PCI_HOST1; stat++)
186 pciWriteConfigReg (stat,
187 PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
188 SELF, CONFIG_SYS_GT_REGS);
194 /* Setup CPU interface paramaters */
195 static void gt_cpu_config (void)
197 cpu_t cpu = get_cpu_type ();
200 /* cpu configuration register */
201 tmp = GTREGREAD (CPU_CONFIGURATION);
203 /* set the SINGLE_CPU bit see MV64360 P.399 */
204 #ifndef CONFIG_SYS_GT_DUAL_CPU /* SINGLE_CPU seems to cause JTAG problems */
205 tmp |= CPU_CONF_SINGLE_CPU;
208 tmp &= ~CPU_CONF_AACK_DELAY_2;
210 tmp |= CPU_CONF_DP_VALID;
211 tmp |= CPU_CONF_AP_VALID;
213 tmp |= CPU_CONF_PIPELINE;
215 GT_REG_WRITE (CPU_CONFIGURATION, tmp); /* Marvell (VXWorks) writes 0x20220FF */
217 /* CPU master control register */
218 tmp = GTREGREAD (CPU_MASTER_CONTROL);
220 tmp |= CPU_MAST_CTL_ARB_EN;
222 if ((cpu == CPU_7400) ||
223 (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
225 tmp |= CPU_MAST_CTL_CLEAN_BLK;
226 tmp |= CPU_MAST_CTL_FLUSH_BLK;
229 /* cleanblock must be cleared for CPUs
230 * that do not support this command (603e, 750)
232 tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
233 tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
235 GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
239 * board_early_init_f.
241 * set up gal. device mappings, etc.
243 int board_early_init_f (void)
248 * set up the GT the way the kernel wants it
249 * the call to move the GT register space will obviously
250 * fail if it has already been done, but we're going to assume
251 * that if it's not at the power-on location, it's where we put
252 * it last time. (huber)
255 my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
257 /* No PCI in first release of Port To_do: enable it. */
261 /* mask all external interrupt sources */
262 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
263 GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
265 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
266 GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
267 /* --------------------- */
268 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
269 GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
270 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
271 GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
272 /* does not exist in MV6436x
273 GT_REG_WRITE(CPU_INT_0_MASK, 0);
274 GT_REG_WRITE(CPU_INT_1_MASK, 0);
275 GT_REG_WRITE(CPU_INT_2_MASK, 0);
276 GT_REG_WRITE(CPU_INT_3_MASK, 0);
277 --------------------- */
280 /* ----- DEVICE BUS SETTINGS ------ */
287 * 3 - Flash checked 32Bit Intel Strata
288 * boot - BootCS checked 8Bit 29LV040B
296 * the dual 7450 module requires burst access to the boot
297 * device, so the serial rom copies the boot device to the
298 * on-board sram on the eval board, and updates the correct
299 * registers to boot from the sram. (device0)
301 if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
304 memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
306 memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
307 memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
308 memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
311 /* configure device timing */
312 #ifdef CONFIG_SYS_DEV0_PAR /* set port parameters for SRAM device module access */
314 GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
317 #ifdef CONFIG_SYS_DEV1_PAR /* set port parameters for RTC device module access */
318 GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
320 #ifdef CONFIG_SYS_DEV2_PAR /* set port parameters for DUART device module access */
321 GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
324 #ifdef CONFIG_SYS_32BIT_BOOT_PAR /* set port parameters for Flash device module access */
325 /* detect if we are booting from the 32 bit flash */
326 if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
327 /* 32 bit boot flash */
328 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
329 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
330 CONFIG_SYS_32BIT_BOOT_PAR);
332 /* 8 bit boot flash */
333 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
334 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
337 /* 8 bit boot flash only */
338 /* GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
345 GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
346 GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
347 GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
348 GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
350 GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
358 /* various things to do after relocation */
373 /* disable the dcache and MMU */
379 void after_reloc (ulong dest_addr, gd_t * gd)
381 /* check to see if we booted from the sram. If so, move things
382 * back to the way they should be. (we're running from main
383 * memory at this point now */
384 if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
385 memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
386 memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
389 /* now, jump to the main ppcboot board init code */
390 board_init_r (gd, dest_addr);
394 /* ------------------------------------------------------------------------- */
397 * Check Board Identity:
399 * right now, assume borad type. (there is just one...after all)
402 int checkboard (void)
406 printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
410 /* utility functions */
411 void debug_led (int led, int mode)
413 volatile int *addr = 0;
414 __maybe_unused int dummy;
419 addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
424 addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
429 addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
433 } else if (mode == 0) {
436 addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
441 addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
446 addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
455 int display_mem_map (void)
458 unsigned int base, size, width;
461 printf ("SD (DDR) RAM\n");
462 for (i = 0; i <= BANK3; i++) {
463 base = memoryGetBankBaseAddress (i);
464 size = memoryGetBankSize (i);
466 printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
467 i, base, size >> 20);
471 /* CPU's PCI windows */
472 for (i = 0; i <= PCI_HOST1; i++) {
473 printf ("\nCPU's PCI %d windows\n", i);
474 base = pciGetSpaceBase (i, PCI_IO);
475 size = pciGetSpaceSize (i, PCI_IO);
476 printf (" IO: base - 0x%08x\tsize - %dM bytes\n", base,
481 /*ronen currently only first PCI MEM is used 3 */ ;
483 base = pciGetSpaceBase (i, j);
484 size = pciGetSpaceSize (i, j);
485 printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
490 printf ("\nDEVICES\n");
491 for (i = 0; i <= DEVICE3; i++) {
492 base = memoryGetDeviceBaseAddress (i);
493 size = memoryGetDeviceSize (i);
494 width = memoryGetDeviceWidth (i) * 8;
495 printf ("DEV %d: base - 0x%08x size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
497 printf ("\t- EXT SRAM (actual - 1M)\n");
499 printf ("\t- RTC\n");
501 printf ("\t- UART\n");
503 printf ("\t- LARGE FLASH\n");
507 base = memoryGetDeviceBaseAddress (BOOT_DEVICE); /* Boot */
508 size = memoryGetDeviceSize (BOOT_DEVICE);
509 width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
510 printf (" BOOT: base - 0x%08x size - %dM bytes\twidth - %d bits\n",
511 base, size >> 20, width);
515 /* DRAM check routines copied from gw8260 */
517 #if defined (CONFIG_SYS_DRAM_TEST)
519 /*********************************************************************/
520 /* NAME: move64() - moves a double word (64-bit) */
523 /* this function performs a double word move from the data at */
524 /* the source pointer to the location at the destination pointer. */
527 /* unsigned long long *src - pointer to data to move */
530 /* unsigned long long *dest - pointer to locate to move data */
535 /* RESTRICTIONS/LIMITATIONS: */
536 /* May cloober fr0. */
538 /*********************************************************************/
539 static void move64 (unsigned long long *src, unsigned long long *dest)
541 asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
542 "stfd 0, 0(4)" /* *dest = fpr0 */
543 : : : "fr0"); /* Clobbers fr0 */
548 #if defined (CONFIG_SYS_DRAM_TEST_DATA)
550 unsigned long long pattern[] = {
551 0xaaaaaaaaaaaaaaaaULL,
552 0xccccccccccccccccULL,
553 0xf0f0f0f0f0f0f0f0ULL,
554 0xff00ff00ff00ff00ULL,
555 0xffff0000ffff0000ULL,
556 0xffffffff00000000ULL,
557 0x00000000ffffffffULL,
558 0x0000ffff0000ffffULL,
559 0x00ff00ff00ff00ffULL,
560 0x0f0f0f0f0f0f0f0fULL,
561 0x3333333333333333ULL,
562 0x5555555555555555ULL,
565 /*********************************************************************/
566 /* NAME: mem_test_data() - test data lines for shorts and opens */
569 /* Tests data lines for shorts and opens by forcing adjacent data */
570 /* to opposite states. Because the data lines could be routed in */
571 /* an arbitrary manner the must ensure test patterns ensure that */
572 /* every case is tested. By using the following series of binary */
573 /* patterns every combination of adjacent bits is test regardless */
576 /* ...101010101010101010101010 */
577 /* ...110011001100110011001100 */
578 /* ...111100001111000011110000 */
579 /* ...111111110000000011111111 */
581 /* Carrying this out, gives us six hex patterns as follows: */
583 /* 0xaaaaaaaaaaaaaaaa */
584 /* 0xcccccccccccccccc */
585 /* 0xf0f0f0f0f0f0f0f0 */
586 /* 0xff00ff00ff00ff00 */
587 /* 0xffff0000ffff0000 */
588 /* 0xffffffff00000000 */
590 /* The number test patterns will always be given by: */
592 /* log(base 2)(number data bits) = log2 (64) = 6 */
594 /* To test for short and opens to other signals on our boards. we */
596 /* test with the 1's complemnt of the paterns as well. */
599 /* Displays failing test pattern */
602 /* 0 - Passed test */
603 /* 1 - Failed test */
605 /* RESTRICTIONS/LIMITATIONS: */
606 /* Assumes only one one SDRAM bank */
608 /*********************************************************************/
609 int mem_test_data (void)
611 unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
612 unsigned long long temp64 = 0;
613 int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
617 for (i = 0; i < num_patterns; i++) {
618 move64 (&(pattern[i]), pmem);
619 move64 (pmem, &temp64);
621 /* hi = (temp64>>32) & 0xffffffff; */
622 /* lo = temp64 & 0xffffffff; */
623 /* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
625 hi = (pattern[i] >> 32) & 0xffffffff;
626 lo = pattern[i] & 0xffffffff;
627 /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
629 if (temp64 != pattern[i]) {
630 printf ("\n Data Test Failed, pattern 0x%08x%08x",
638 #endif /* CONFIG_SYS_DRAM_TEST_DATA */
640 #if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
641 /*********************************************************************/
642 /* NAME: mem_test_address() - test address lines */
645 /* This function performs a test to verify that each word im */
646 /* memory is uniquly addressable. The test sequence is as follows: */
648 /* 1) write the address of each word to each word. */
649 /* 2) verify that each location equals its address */
652 /* Displays failing test pattern and address */
655 /* 0 - Passed test */
656 /* 1 - Failed test */
658 /* RESTRICTIONS/LIMITATIONS: */
661 /*********************************************************************/
662 int mem_test_address (void)
664 volatile unsigned int *pmem =
665 (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
666 const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
669 /* write address to each location */
670 for (i = 0; i < size; i++) {
674 /* verify each loaction */
675 for (i = 0; i < size; i++) {
677 printf ("\n Address Test Failed at 0x%x", i);
683 #endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
685 #if defined (CONFIG_SYS_DRAM_TEST_WALK)
686 /*********************************************************************/
687 /* NAME: mem_march() - memory march */
690 /* Marches up through memory. At each location verifies rmask if */
691 /* read = 1. At each location write wmask if write = 1. Displays */
692 /* failing address and pattern. */
695 /* volatile unsigned long long * base - start address of test */
696 /* unsigned int size - number of dwords(64-bit) to test */
697 /* unsigned long long rmask - read verify mask */
698 /* unsigned long long wmask - wrtie verify mask */
699 /* short read - verifies rmask if read = 1 */
700 /* short write - writes wmask if write = 1 */
703 /* Displays failing test pattern and address */
706 /* 0 - Passed test */
707 /* 1 - Failed test */
709 /* RESTRICTIONS/LIMITATIONS: */
712 /*********************************************************************/
713 int mem_march (volatile unsigned long long *base,
715 unsigned long long rmask,
716 unsigned long long wmask, short read, short write)
719 unsigned long long temp = 0;
720 unsigned int hitemp, lotemp, himask, lomask;
722 for (i = 0; i < size; i++) {
724 /* temp = base[i]; */
725 move64 ((unsigned long long *) &(base[i]), &temp);
727 hitemp = (temp >> 32) & 0xffffffff;
728 lotemp = temp & 0xffffffff;
729 himask = (rmask >> 32) & 0xffffffff;
730 lomask = rmask & 0xffffffff;
732 printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
737 /* base[i] = wmask; */
738 move64 (&wmask, (unsigned long long *) &(base[i]));
743 #endif /* CONFIG_SYS_DRAM_TEST_WALK */
745 /*********************************************************************/
746 /* NAME: mem_test_walk() - a simple walking ones test */
749 /* Performs a walking ones through entire physical memory. The */
750 /* test uses as series of memory marches, mem_march(), to verify */
751 /* and write the test patterns to memory. The test sequence is as */
753 /* 1) march writing 0000...0001 */
754 /* 2) march verifying 0000...0001 , writing 0000...0010 */
755 /* 3) repeat step 2 shifting masks left 1 bit each time unitl */
756 /* the write mask equals 1000...0000 */
757 /* 4) march verifying 1000...0000 */
758 /* The test fails if any of the memory marches return a failure. */
761 /* Displays which pass on the memory test is executing */
764 /* 0 - Passed test */
765 /* 1 - Failed test */
767 /* RESTRICTIONS/LIMITATIONS: */
770 /*********************************************************************/
771 int mem_test_walk (void)
773 unsigned long long mask;
774 volatile unsigned long long *pmem =
775 (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
776 const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
782 printf ("Initial Pass");
783 mem_march (pmem, size, 0x0, 0x1, 0, 1);
785 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
788 printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
790 for (i = 0; i < 63; i++) {
791 printf ("Pass %2d", i + 2);
792 if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
793 /*printf("mask: 0x%x, pass: %d, ", mask, i); */
797 printf ("\b\b\b\b\b\b\b");
800 printf ("Last Pass");
801 if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
802 /* printf("mask: 0x%x", mask); */
805 printf ("\b\b\b\b\b\b\b\b\b");
807 printf ("\b\b\b\b\b\b\b\b\b");
812 /*********************************************************************/
813 /* NAME: testdram() - calls any enabled memory tests */
816 /* Runs memory tests if the environment test variables are set to */
820 /* testdramdata - If set to 'y', data test is run. */
821 /* testdramaddress - If set to 'y', address test is run. */
822 /* testdramwalk - If set to 'y', walking ones test is run */
828 /* 0 - Passed test */
829 /* 1 - Failed test */
831 /* RESTRICTIONS/LIMITATIONS: */
834 /*********************************************************************/
837 int rundata, runaddress, runwalk;
839 rundata = getenv_yesno("testdramdata") == 1;
840 runaddress = getenv_yesno("testdramaddress") == 1;
841 runwalk = getenv_yesno("testdramwalk") == 1;
844 /* runaddress = 0; */
847 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
848 printf ("Testing RAM from 0x%08x to 0x%08x ... (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
850 #ifdef CONFIG_SYS_DRAM_TEST_DATA
852 printf ("Test DATA ... ");
853 if (mem_test_data () == 1) {
854 printf ("failed \n");
860 #ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
861 if (runaddress == 1) {
862 printf ("Test ADDRESS ... ");
863 if (mem_test_address () == 1) {
864 printf ("failed \n");
870 #ifdef CONFIG_SYS_DRAM_TEST_WALK
872 printf ("Test WALKING ONEs ... ");
873 if (mem_test_walk () == 1) {
874 printf ("failed \n");
880 if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
886 #endif /* CONFIG_SYS_DRAM_TEST */
888 /* ronen - the below functions are used by the bootm function */
889 /* - we map the base register to fbe00000 (same mapping as in the LSP) */
890 /* - we turn off the RX gig dmas - to prevent the dma from overunning */
891 /* the kernel data areas. */
892 /* - we diable and invalidate the icache and dcache. */
893 void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
897 temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
898 if ((temp & 0xffff) == new_loc >> 16)
901 temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
902 0xffff0000) | (new_loc >> 16);
904 out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
906 while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
908 (INTERNAL_SPACE_DECODE)))))
913 void board_prebootm_init ()
916 /* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
917 GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
919 /* Stop GigE Rx DMA engines */
920 GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
921 GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00);
922 /* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */
924 /* Relocate MV64360 internal regs */
925 my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
931 int board_eth_init(bd_t *bis)
934 ret = pci_eth_init(bis);
936 ret = mv6436x_eth_initialize(bis);