2 /*------------------------------------------------------*/
3 /* TERON Articia / SDRAM Init */
4 /*------------------------------------------------------*/
6 * XD_CTL = 0x81000000 (0x74)
8 * HBUS_ACC_CTL_0 &= 0xFFFFFDFF (0x5c)
9 /* host bus access ctl reg 2(5e) */
10 /* set - CPU read from memory data one clock after data is latched */
12 * GLOBL_INFO_0 |= 0x00004000 (0x50)
13 /* global info register 2 (52), AGP/PCI bus 1 arbiter is addressed in Articia S */
15 PCI_1_SB_CONFIG_0 |= 0x00000400 (0x80d0)
16 /* PCI1 side band config reg 2 (d2), enable read acces while write buffer not empty */
18 MEM_RAS_CTL_0 |= 0x3f000000 (0xcc)
20 /* RAS park control reg 0(cc), park access enable is set */
22 HOST_RDBUF_CTL |= 0x10000000 (0x70)
24 /* host read buffer control reg, enable prefetch for CPU read from DRAM control */
26 HBUS_ACC_CTL_0 |= 0x0100001f (0x5c)
28 /* host bus access control register, enable CPU address bus pipe control */
29 /* two outstanding requests, *** changed to 2 from 3 */
30 /* enable line merge write control for CPU write to system memory, PCI 1 */
31 /* and PCI 0 bus memory; enable page merge write control for write to */
32 /* PCI bus 0 & bus 1 memory */
34 SRAM_CTL |= 0x00004000 (0xc8)
36 /* DRAM detail timing control register 1 (ca), bit 3 set to 0 */
37 /* DRAM start access latency control - wait for one clock */
38 /* ff9f changed to ffbf */
40 DIM0_TIM_CTL_0 = 0x737d737d (0xc9)
41 /* DRAM timing control for dimm0 & dimm1; set wait one clock */
42 /* cycle for next data access */
44 DIM2_TIM_CTL_0 = 0x737d737d (0xca)
45 /* DRAM timing control for dimm2 & dimm3; set wait one clock */
46 /* cycle for next data access */
48 DIM0_BNK0_CTL_0 = BNK0_RAM_SIZ_128MB (0x90)
49 /* set dimm0 bank0 for 128 MB */
51 DIM0_BNK1_CTL_0 = BNK1_RAM_SIZ_128MB (0x94)
52 /* set dimm0 for bank1 */
54 DIM0_TIM_CTL_0 = 0xf3bf0000 (0xc9)
55 /* dimm0 timing control register; RAS - CAS latency - 4 clock */
56 /* CAS access latency - 3 wait; pre-charge latency - 3 wait */
57 /* pre-charge command period control - 5 clock; wait one clock */
58 /* cycle for next data access; read to write access latency control */
59 /* - 2 clock cycles */
61 DRAM_GBL_CTL_0 |= 0x00000100 (0xc0)
63 /* memory global control register - support buffer sdram on bank 0 */
65 DRAM_ECC_CTL_0 |= 0x00260000 (0xc4)
67 /* enable ECC; enable read, modify, write control */
69 DRAM_REF_CTL_0 = DRAM_REF_DATA (0xb8)
70 /* set DRAM refresh parameters *** changed to 00940100 */
78 DRAM_ECC_CTL_0 |= 0x20243280 (0xc4)
80 /* for SDRAM bank 0 */
82 DRAM_ECC_CTL_0 |= 0x20243290 (0xc4) ?
83 /* for SDRAM bank 1 */
86 /* Additional Stuff...*/
88 GLOBL_CTRL |= 0x20000b00 (0x54)
90 PCI_0_SB_CONFIG |= 0x04100007 (0xd0)
91 /* PCI 0 Side band config reg*/
93 0x8000083c |= 0x00080000
94 /* Disable VGA decode on PCI Bus 1 */
97 /*End Additional Stuff..*/
99 /*--------------------------------------------------------------*/
100 /* TERON serial port initialization code */
101 /*--------------------------------------------------------------*/
103 0x84380080 |= 0x00030000
104 /* enable super IO configuration VIA chip Register 85 */
105 /* Enable super I/O config mode */
112 /* enable com1 & com2, parallel port disabled */
116 /* let's make com1 base as 0x3f8 */
123 /* let's make com2 base as 0x2f8 */
127 0x84380080 &= 0xfffdffff
128 /* closing super IO configuration VIA chip Register 85 */
131 /* -------------------------------*/
135 /*latch enable word length -8 bit */ /* set mslab bit */
138 /* set baud rate lsb for 9600 baud */
141 /* set baud rate msb for 9600 baud */
146 /*--------------------------------------------------------------*/
147 /* END TERON Serial Port Initialization Code */
148 /*--------------------------------------------------------------*/
151 /*--------------------------------------------------------------*/
152 /* END TERON Articia / SDRAM Initialization code */
153 /*--------------------------------------------------------------*/
155 Proposed from Documentation:
157 write dmem 0xfec00cf8 0x50000080
158 write dmem 0xfee00cfc 0xc0305411
160 Writes to index 0x50-0x53.
161 0x50: Global Information Register 0
162 0xC0 = Little Endian CPU, Sequential order Burst
163 0x51: Global Information Register 1
164 Read only, 0x30 = Provides PowerPC and X86 support
165 0x52: Global Information Register 2
166 0x05 = 64/128 bit CPU bus support
167 0x53: Global Information Register 3
168 0x80 = PCI Bus 0 grant active time is 1 clock after REQ# deasserted
170 write dmem 0xfec00cf8 0x5c000080
171 write dmem 0xfee00cfc 0xb300011F
173 write dmem 0xfec00cf8 0xc8000080
174 write dmem 0xfee00cfc 0x0020f100
176 write dmem 0xfec00cf8 0x90000080
177 write dmem 0xfee00cfc 0x007fe700
179 write dmem 0xfec00cf8 0x9400080
180 write dmem 0xfee00cfc 0x007fe700
182 write dmem 0xfec00cf8 0xb0000080
183 write dmem 0xfee00cfc 0x737d737d
185 write dmem 0xfec00cf8 0xb4000080
186 write dmem 0xfee00cfc 0x737d737d
188 write dmem 0xfec00cf8 0xc0000080
189 write dmem 0xfee00cfc 0x40005500
191 write dmem 0xfec00cf8 0xb8000080
192 write dmem 0xfee00cfc 0x00940100
194 write dmem 0xfec00cf8 0xc4000080
195 write dmem 0xfee00cfc 0x00003280
197 write dmem 0xfec00cf8 0xc4000080
198 write dmem 0xfee00cfc 0x00003290