3 * Adam Kowalczyk, ACK Software Controls Inc. akowalczyk@cogeco.ca
5 * Some portions taken from 3c59x.c Written 1996-1999 by Donald Becker.
7 * Outline of the program based on eepro100.c which is
10 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 /* 3Com Ethernet PCI definitions*/
39 // #define PCI_VENDOR_ID_3COM 0x10B7
40 #define PCI_DEVICE_ID_3COM_3C905C 0x9200
42 /* 3Com Commands, top 5 bits are command and bottom 11 bits are parameters */
44 #define TotalReset (0<<11)
45 #define SelectWindow (1<<11)
46 #define StartCoax (2<<11)
47 #define RxDisable (3<<11)
48 #define RxEnable (4<<11)
49 #define RxReset (5<<11)
50 #define UpStall (6<<11)
51 #define UpUnstall (6<<11)+1
52 #define DownStall (6<<11)+2
53 #define DownUnstall (6<<11)+3
54 #define RxDiscard (8<<11)
55 #define TxEnable (9<<11)
56 #define TxDisable (10<<11)
57 #define TxReset (11<<11)
58 #define FakeIntr (12<<11)
59 #define AckIntr (13<<11)
60 #define SetIntrEnb (14<<11)
61 #define SetStatusEnb (15<<11)
62 #define SetRxFilter (16<<11)
63 #define SetRxThreshold (17<<11)
64 #define SetTxThreshold (18<<11)
65 #define SetTxStart (19<<11)
66 #define StartDMAUp (20<<11)
67 #define StartDMADown (20<<11)+1
68 #define StatsEnable (21<<11)
69 #define StatsDisable (22<<11)
70 #define StopCoax (23<<11)
71 #define SetFilterBit (25<<11)
73 /* The SetRxFilter command accepts the following classes */
80 /* 3Com status word defnitions */
82 #define IntLatch 0x0001
83 #define HostError 0x0002
84 #define TxComplete 0x0004
85 #define TxAvailable 0x0008
86 #define RxComplete 0x0010
87 #define RxEarly 0x0020
89 #define StatsFull 0x0080
90 #define DMADone (1<<8)
91 #define DownComplete (1<<9)
92 #define UpComplete (1<<10)
93 #define DMAInProgress (1<<11) /* DMA controller is still busy.*/
94 #define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/
96 /* Polling Registers */
101 /* Register window 0 offets */
103 #define Wn0EepromCmd 10 /* Window 0: EEPROM command register. */
104 #define Wn0EepromData 12 /* Window 0: EEPROM results register. */
105 #define IntrStatus 0x0E /* Valid in all windows. */
107 /* Register window 0 EEPROM bits */
109 #define EEPROM_Read 0x80
110 #define EEPROM_WRITE 0x40
111 #define EEPROM_ERASE 0xC0
112 #define EEPROM_EWENB 0x30 /* Enable erasing/writing for 10 msec. */
113 #define EEPROM_EWDIS 0x00 /* Disable EWENB before 10 msec timeout. */
115 /* EEPROM locations. */
121 #define EtherLink3ID 7
124 #define NodeAddr01 10
125 #define NodeAddr23 11
126 #define NodeAddr45 12
127 #define DriverTune 13
130 /* Register window 1 offsets, the window used in normal operation */
134 #define RxErrors 0x14
135 #define RxStatus 0x18
137 #define TxStatus 0x1B
138 #define TxFree 0x1C /* Remaining free bytes in Tx buffer. */
140 /* Register Window 2 */
142 #define Wn2_ResetOptions 12
144 /* Register Window 3: MAC/config bits */
146 #define Wn3_Config 0 /* Internal Configuration */
147 #define Wn3_MAC_Ctrl 6
148 #define Wn3_Options 8
150 #define BFEXT(value, offset, bitcount) \
151 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
153 #define BFINS(lhs, rhs, offset, bitcount) \
154 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
155 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
157 #define RAM_SIZE(v) BFEXT(v, 0, 3)
158 #define RAM_WIDTH(v) BFEXT(v, 3, 1)
159 #define RAM_SPEED(v) BFEXT(v, 4, 2)
160 #define ROM_SIZE(v) BFEXT(v, 6, 2)
161 #define RAM_SPLIT(v) BFEXT(v, 16, 2)
162 #define XCVR(v) BFEXT(v, 20, 4)
163 #define AUTOSELECT(v) BFEXT(v, 24, 1)
165 /* Register Window 4: Xcvr/media bits */
167 #define Wn4_FIFODiag 4
168 #define Wn4_NetDiag 6
169 #define Wn4_PhysicalMgmt 8
172 #define Media_SQE 0x0008 /* Enable SQE error counting for AUI. */
173 #define Media_10TP 0x00C0 /* Enable link beat and jabber for 10baseT. */
174 #define Media_Lnk 0x0080 /* Enable just link beat for 100TX/100FX. */
175 #define Media_LnkBeat 0x0800
177 /* Register Window 7: Bus Master control */
179 #define Wn7_MasterAddr 0
180 #define Wn7_MasterLen 6
181 #define Wn7_MasterStatus 12
183 /* Boomerang bus master control registers. */
185 #define PktStatus 0x20
186 #define DownListPtr 0x24
187 #define FragAddr 0x28
189 #define TxFreeThreshold 0x2f
190 #define UpPktStatus 0x30
191 #define UpListPtr 0x38
193 /* The Rx and Tx descriptor lists. */
195 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
196 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
198 struct rx_desc_3com {
199 u32 next; /* Last entry points to 0 */
200 u32 status; /* FSH -> Frame Start Header */
201 u32 addr; /* Up to 63 addr/len pairs possible */
202 u32 length; /* Set LAST_FRAG to indicate last pair */
205 /* Values for the Rx status entry. */
207 #define RxDComplete 0x00008000
208 #define RxDError 0x4000
209 #define IPChksumErr (1<<25)
210 #define TCPChksumErr (1<<26)
211 #define UDPChksumErr (1<<27)
212 #define IPChksumValid (1<<29)
213 #define TCPChksumValid (1<<30)
214 #define UDPChksumValid (1<<31)
216 struct tx_desc_3com {
217 u32 next; /* Last entry points to 0 */
218 u32 status; /* bits 0:12 length, others see below */
223 /* Values for the Tx status entry. */
225 #define CRCDisable 0x2000
226 #define TxDComplete 0x8000
227 #define AddIPChksum 0x02000000
228 #define AddTCPChksum 0x04000000
229 #define AddUDPChksum 0x08000000
230 #define TxIntrUploaded 0x80000000 /* IRQ when in FIFO, but maybe not sent. */
234 #define XCVR_10baseT 0
236 #define XCVR_10baseTOnly 2
237 #define XCVR_10base2 3
238 #define XCVR_100baseTx 4
239 #define XCVR_100baseFx 5
242 #define XCVR_ExtMII 9
243 #define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */
245 struct descriptor { /* A generic descriptor. */
246 u32 next; /* Last entry points to 0 */
247 u32 status; /* FSH -> Frame Start Header */
248 u32 addr; /* Up to 63 addr/len pairs possible */
249 u32 length; /* Set LAST_FRAG to indicate last pair */
252 /* Misc. definitions */
254 #define NUM_RX_DESC PKTBUFSRX * 10
255 #define NUM_TX_DESC 1 /* Number of TX descriptors */
257 #define TOUT_LOOP 1000000
261 #define EL3WINDOW(dev, win_num) ETH_OUTW(dev, SelectWindow + (win_num), EL3_CMD)
263 #define EL3_STATUS 0x0e
269 #define PRINTF(fmt,args...) printf (fmt ,##args)
271 #define PRINTF(fmt,args...)
275 static struct rx_desc_3com *rx_ring; /* RX descriptor ring */
276 static struct tx_desc_3com *tx_ring; /* TX descriptor ring */
277 static u8 rx_buffer[NUM_RX_DESC][PKTSIZE_ALIGN]; /* storage for the incoming messages */
278 static int rx_next = 0; /* RX descriptor ring pointer */
279 static int tx_next = 0; /* TX descriptor ring pointer */
280 static int tx_threshold;
282 static void init_rx_ring(struct eth_device* dev);
283 static void purge_tx_ring(struct eth_device* dev);
285 static void read_hw_addr(struct eth_device* dev, bd_t * bis);
287 static int eth_3com_init(struct eth_device* dev, bd_t *bis);
288 static int eth_3com_send(struct eth_device* dev, volatile void *packet, int length);
289 static int eth_3com_recv(struct eth_device* dev);
290 static void eth_3com_halt(struct eth_device* dev);
292 #define io_to_phys(a) pci_io_to_phys((pci_dev_t)dev->priv, a)
293 #define phys_to_io(a) pci_phys_to_io((pci_dev_t)dev->priv, a)
294 #define mem_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
295 #define phys_to_mem(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
297 static inline int ETH_INL(struct eth_device* dev, u_long addr)
299 __asm volatile ("eieio");
300 return le32_to_cpu(*(volatile u32 *)io_to_phys(addr + dev->iobase));
303 static inline int ETH_INW(struct eth_device* dev, u_long addr)
305 __asm volatile ("eieio");
306 return le16_to_cpu(*(volatile u16 *)io_to_phys(addr + dev->iobase));
309 static inline int ETH_INB(struct eth_device* dev, u_long addr)
311 __asm volatile ("eieio");
312 return *(volatile u8 *)io_to_phys(addr + dev->iobase);
315 static inline void ETH_OUTB(struct eth_device* dev, int command, u_long addr)
317 *(volatile u8 *)io_to_phys(addr + dev->iobase) = command;
318 __asm volatile ("eieio");
321 static inline void ETH_OUTW(struct eth_device* dev, int command, u_long addr)
323 *(volatile u16 *)io_to_phys(addr + dev->iobase) = cpu_to_le16(command);
324 __asm volatile ("eieio");
327 static inline void ETH_OUTL(struct eth_device* dev, int command, u_long addr)
329 *(volatile u32 *)io_to_phys(addr + dev->iobase) = cpu_to_le32(command);
330 __asm volatile ("eieio");
333 static inline int ETH_STATUS(struct eth_device* dev)
335 __asm volatile ("eieio");
336 return le16_to_cpu(*(volatile u16 *)io_to_phys(EL3_STATUS + dev->iobase));
339 static inline void ETH_CMD(struct eth_device* dev, int command)
341 *(volatile u16 *)io_to_phys(EL3_CMD + dev->iobase) = cpu_to_le16(command);
342 __asm volatile ("eieio");
345 /* Command register is always in the same spot in all the register windows */
346 /* This function issues a command and waits for it so complete by checking the CmdInProgress bit */
348 static int issue_and_wait(struct eth_device* dev, int command)
353 ETH_CMD(dev, command);
354 for (i = 0; i < 2000; i++) {
355 status = ETH_STATUS(dev);
356 //printf ("Issue: status 0x%4x.\n", status);
357 if (!(status & CmdInProgress))
361 /* OK, that didn't work. Do it the slow way. One second */
362 for (i = 0; i < 100000; i++) {
363 status = ETH_STATUS(dev);
364 //printf ("Issue: status 0x%4x.\n", status);
368 PRINTF("Ethernet command: 0x%4x did not complete! Status: 0x%4x\n", command, ETH_STATUS(dev) );
372 /* Determine network media type and set up 3com accordingly */
373 /* I think I'm going to start with something known first like 10baseT */
375 static int auto_negotiate(struct eth_device* dev)
381 // Wait for Auto negotiation to complete
382 for (i = 0; i <= 1000; i++)
384 if (ETH_INW(dev, 2) & 0x04)
390 PRINTF("Error: Auto negotiation failed\n");
400 void eth_interrupt(struct eth_device *dev)
402 u16 status = ETH_STATUS(dev);
404 printf("eth0: status = 0x%04x\n", status);
406 if (!(status & IntLatch))
411 ETH_CMD(dev, AckIntr | (1<<6));
412 printf("Acknowledged Interrupt command\n");
415 if (status & DownComplete)
417 ETH_CMD(dev, AckIntr | DownComplete);
418 printf("Acknowledged DownComplete\n");
421 if (status & UpComplete)
423 ETH_CMD(dev, AckIntr | UpComplete);
424 printf("Acknowledged UpComplete\n");
427 ETH_CMD(dev, AckIntr | IntLatch);
428 printf("Acknowledged IntLatch\n");
431 int eth_3com_initialize(bd_t *bis)
433 u32 eth_iobase = 0, status;
434 int card_number = 0, ret;
435 struct eth_device* dev;
439 s = getenv("3com_base");
441 /* Find ethernet controller on the PCI bus */
443 if ((devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0)) < 0)
445 PRINTF("Error: Cannot find the ethernet device on the PCI bus\n");
451 unsigned long base = atoi(s);
452 pci_write_config_dword(devno, PCI_BASE_ADDRESS_0, base | 0x01);
455 ret = pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, ð_iobase);
458 PRINTF("eth: 3Com Found at Address: 0x%x\n", eth_iobase);
460 pci_write_config_dword(devno, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
462 /* Check if I/O accesses and Bus Mastering are enabled */
464 ret = pci_read_config_dword(devno, PCI_COMMAND, &status);
466 if (!(status & PCI_COMMAND_IO))
468 printf("Error: Cannot enable IO access.\n");
472 if (!(status & PCI_COMMAND_MEMORY))
474 printf("Error: Cannot enable MEMORY access.\n");
478 if (!(status & PCI_COMMAND_MASTER))
480 printf("Error: Cannot enable Bus Mastering.\n");
484 dev = (struct eth_device*) malloc(sizeof(*dev)); //struct eth_device));
486 sprintf(dev->name, "3Com 3c920c#%d", card_number);
487 dev->iobase = eth_iobase;
488 dev->priv = (void*) devno;
489 dev->init = eth_3com_init;
490 dev->halt = eth_3com_halt;
491 dev->send = eth_3com_send;
492 dev->recv = eth_3com_recv;
497 /* char interrupt; */
498 /* devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */
499 /* pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */
501 /* printf("Installing eth0 interrupt handler to %d\n", interrupt); */
502 /* irq_install_handler(interrupt, eth_interrupt, dev); */
507 /* Set the latency timer for value */
508 s = getenv("3com_latency");
511 ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, (unsigned char)atoi(s));
513 else ret = pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x0a);
515 read_hw_addr(dev, bis); /* get the MAC address from Window 2*/
517 /* Reset the ethernet controller */
519 PRINTF ("Issuing reset command....\n");
520 if (!issue_and_wait(dev, TotalReset))
522 printf("Error: Cannot reset ethernet controller.\n");
526 PRINTF ("Ethernet controller reset.\n");
528 /* allocate memory for rx and tx rings */
530 if(!(rx_ring = memalign(sizeof(struct rx_desc_3com) * NUM_RX_DESC, 16)))
532 PRINTF ("Cannot allocate memory for RX_RING.....\n");
536 if (!(tx_ring = memalign(sizeof(struct tx_desc_3com) * NUM_TX_DESC, 16)))
538 PRINTF ("Cannot allocate memory for TX_RING.....\n");
547 static int eth_3com_init(struct eth_device* dev, bd_t *bis)
551 u16 status_enable, intr_enable;
552 struct descriptor *ias_cmd;
554 /* Determine what type of network the machine is connected to */
555 /* presently drops the connect to 10Mbps */
557 if (!auto_negotiate(dev))
559 printf("Error: Cannot determine network media.\n");
563 issue_and_wait(dev, TxReset);
564 issue_and_wait(dev, RxReset|0x04);
566 /* Switch to register set 7 for normal use. */
569 /* Initialize Rx and Tx rings */
574 ETH_CMD(dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
576 issue_and_wait(dev,SetTxStart|0x07ff);
578 /* Below sets which indication bits to be seen. */
580 status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6);
581 ETH_CMD(dev, status_enable);
583 /* Below sets no bits are to cause an interrupt since this is just polling */
585 intr_enable = SetIntrEnb;
586 // intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6);
587 ETH_CMD(dev, intr_enable);
588 ETH_OUTB(dev, 127, UpPoll);
590 /* Ack all pending events, and set active indicator mask */
592 ETH_CMD(dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
593 ETH_CMD(dev, intr_enable);
595 /* Tell the adapter where the RX ring is located */
597 issue_and_wait(dev,UpStall); /* Stall and set the UplistPtr */
598 ETH_OUTL(dev, (u32)&rx_ring[rx_next], UpListPtr);
599 ETH_CMD(dev, RxEnable); /* Enable the receiver. */
600 issue_and_wait(dev,UpUnstall);
602 /* Send the Individual Address Setup frame */
605 tx_next = ((tx_next+1) % NUM_TX_DESC);
607 ias_cmd = (struct descriptor *)&tx_ring[tx_cur];
608 ias_cmd->status = cpu_to_le32(1<<31); /* set DnIndicate bit. */
610 ias_cmd->addr = cpu_to_le32((u32)&bis->bi_enetaddr[0]);
611 ias_cmd->length = cpu_to_le32(6 | LAST_FRAG);
613 /* Tell the adapter where the TX ring is located */
615 ETH_CMD(dev, TxEnable); /* Enable transmitter. */
616 issue_and_wait(dev, DownStall); /* Stall and set the DownListPtr. */
617 ETH_OUTL(dev, (u32)&tx_ring[tx_cur], DownListPtr);
618 issue_and_wait(dev, DownUnstall);
619 for (i=0; !(ETH_STATUS(dev) & DownComplete); i++)
623 PRINTF("TX Ring status (Init): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status));
624 PRINTF("ETH_STATUS: 0x%x\n", ETH_STATUS(dev));
628 if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */
630 ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
631 issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
632 ETH_OUTL(dev, 0, DownListPtr);
633 issue_and_wait(dev, DownUnstall);
641 int eth_3com_send(struct eth_device* dev, volatile void *packet, int length)
648 PRINTF("eth: bad packet size: %d\n", length);
653 tx_next = (tx_next+1) % NUM_TX_DESC;
655 tx_ring[tx_cur].status = cpu_to_le32(1<<31); /* set DnIndicate bit */
656 tx_ring[tx_cur].next = 0;
657 tx_ring[tx_cur].addr = cpu_to_le32(((u32) packet));
658 tx_ring[tx_cur].length = cpu_to_le32(length | LAST_FRAG);
660 /* Send the packet */
662 issue_and_wait(dev, DownStall); /* stall and set the DownListPtr */
663 ETH_OUTL(dev, (u32) &tx_ring[tx_cur], DownListPtr);
664 issue_and_wait(dev, DownUnstall);
666 for (i=0; !(ETH_STATUS(dev) & DownComplete); i++)
670 PRINTF("TX Ring status (send): 0x%4x\n", le32_to_cpu(tx_ring[tx_cur].status));
674 if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */
676 ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
677 issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
678 ETH_OUTL(dev, 0, DownListPtr);
679 issue_and_wait(dev, DownUnstall);
686 void PrintPacket (uchar *packet, int length)
691 printf ("Printing packet of length %x.\n\n", length);
693 for (loop = 1; loop <= length; loop++)
695 printf ("%2x ", *ptr++);
701 int eth_3com_recv(struct eth_device* dev)
705 int rx_prev, length = 0;
707 while (!(ETH_STATUS(dev) & UpComplete)) /* wait on receipt of packet */
710 status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */
712 while (status & (1<<15))
714 /* A packet has been received */
716 if (status & (1<<15))
718 /* A valid frame received */
720 length = le32_to_cpu(rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */
722 /* Pass the packet up to the protocol layers */
724 NetReceive((uchar *)le32_to_cpu(rx_ring[rx_next].addr), length);
725 rx_ring[rx_next].status = 0; /* clear the status word */
726 ETH_CMD(dev, AckIntr | UpComplete);
727 issue_and_wait(dev, UpUnstall);
730 if (stat & HostError)
732 /* There was an error */
734 printf("Rx error status: 0x%4x\n", stat);
740 rx_next = (rx_next + 1) % NUM_RX_DESC;
741 stat = ETH_STATUS(dev); /* register status */
742 status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */
749 void eth_3com_halt(struct eth_device* dev)
756 issue_and_wait(dev, DownStall); /* shut down transmit and receive */
757 issue_and_wait(dev, UpStall);
758 issue_and_wait(dev, RxDisable);
759 issue_and_wait(dev, TxDisable);
761 // free(tx_ring); /* release memory allocated to the DPD and UPD rings */
768 static void init_rx_ring(struct eth_device* dev)
772 PRINTF("Initializing rx_ring. rx_buffer = %p\n", rx_buffer);
773 issue_and_wait(dev, UpStall);
775 for (i = 0; i < NUM_RX_DESC; i++)
777 rx_ring[i].next = cpu_to_le32(((u32) &rx_ring[(i+1) % NUM_RX_DESC]));
778 rx_ring[i].status = 0;
779 rx_ring[i].addr = cpu_to_le32(((u32) &rx_buffer[i][0]));
780 rx_ring[i].length = cpu_to_le32(PKTSIZE_ALIGN | LAST_FRAG);
785 static void purge_tx_ring(struct eth_device* dev)
789 PRINTF("Purging tx_ring.\n");
793 for (i = 0; i < NUM_TX_DESC; i++)
796 tx_ring[i].status = 0;
798 tx_ring[i].length = 0;
802 static void read_hw_addr(struct eth_device* dev, bd_t *bis)
804 u8 hw_addr[ETH_ALEN];
805 unsigned int eeprom[0x40];
806 unsigned int checksum = 0;
809 /* Read the station address from the EEPROM. */
812 for (i = 0; i < 0x40; i++)
814 ETH_OUTW(dev, EEPROM_Read + i, Wn0EepromCmd);
815 /* Pause for at least 162 us. for the read to take place. */
816 for (timer = 10; timer >= 0; timer--)
819 if ((ETH_INW(dev, Wn0EepromCmd) & 0x8000) == 0)
822 eeprom[i] = ETH_INW(dev, Wn0EepromData);
825 /* Checksum calculation. I'm not sure about this part and there seems to be a bug on the 3com side of things */
827 for (i = 0; i < 0x21; i++)
828 checksum ^= eeprom[i];
829 checksum = (checksum ^ (checksum >> 8)) & 0xff;
831 if (checksum != 0xbb)
832 printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum);
834 for (i = 0, j = 0; i < 3; i++)
836 hw_addr[j++] = (u8)((eeprom[i+10] >> 8) & 0xff);
837 hw_addr[j++] = (u8)(eeprom[i+10] & 0xff);
840 /* MAC Address is in window 2, write value from EEPROM to window 2 */
843 for (i = 0; i < 6; i++)
844 ETH_OUTB(dev, hw_addr[i], i);
846 for (j = 0; j < ETH_ALEN; j+=2)
848 hw_addr[j] = (u8)(ETH_INW(dev, j) & 0xff);
849 hw_addr[j+1] = (u8)((ETH_INW(dev, j) >> 8) & 0xff);
852 for (i=0;i<ETH_ALEN;i++)
854 if (hw_addr[i] != bis->bi_enetaddr[i])
856 /* printf("Warning: HW address don't match:\n"); */
857 /* printf("Address in 3Com Window 2 is " */
858 /* "%02X:%02X:%02X:%02X:%02X:%02X\n", */
859 /* hw_addr[0], hw_addr[1], hw_addr[2], */
860 /* hw_addr[3], hw_addr[4], hw_addr[5]); */
861 /* printf("Address used by U-Boot is " */
862 /* "%02X:%02X:%02X:%02X:%02X:%02X\n", */
863 /* bis->bi_enetaddr[0], bis->bi_enetaddr[1], */
864 /* bis->bi_enetaddr[2], bis->bi_enetaddr[3], */
865 /* bis->bi_enetaddr[4], bis->bi_enetaddr[5]); */
868 if (bis->bi_enetaddr[0] == 0 && bis->bi_enetaddr[1] == 0 &&
869 bis->bi_enetaddr[2] == 0 && bis->bi_enetaddr[3] == 0 &&
870 bis->bi_enetaddr[4] == 0 && bis->bi_enetaddr[5] == 0)
873 sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X",
874 hw_addr[0], hw_addr[1], hw_addr[2],
875 hw_addr[3], hw_addr[4], hw_addr[5]);
876 setenv("ethaddr", buffer);
881 for(i=0; i<ETH_ALEN; i++) dev->enetaddr[i] = hw_addr[i];