5 #define GLOBALINFO0 0x50
6 #define GLOBALINFO0_BO (1<<7)
7 #define GLOBALINFO2_B1ARBITER (1<<6)
9 #define HBUSACR2_BURST (1<<0)
10 #define HBUSACR2_LAT (1<<1)
12 #define RECEIVER_HOLDING 0
13 #define TRANSMITTER_HOLDING 0
14 #define INTERRUPT_ENABLE 1
15 #define INTERRUPT_STATUS 2
16 #define FIFO_CONTROL 2
17 #define LINE_CONTROL 3
18 #define MODEM_CONTROL 4
20 #define MODEM_STATUS 6
23 #define DIVISOR_LATCH_LSB 0
24 #define DIVISOR_LATCH_MSB 1
25 #define PRESCALER_DIVISION 5
27 #define UART(x) (0x3f8+(x))
29 #define GLOBALINFO0 0x50
30 #define GLOBALINFO0_BO (1<<7)
31 #define GLOBALINFO2_B1ARBITER (1<<6)
33 #define HBUSACR2_BURST (1<<0)
34 #define HBUSACR2_LAT (1<<1)
36 #define SUPERIO_1 ((7 << 3) | (0))
37 #define SUPERIO_2 ((7 << 3) | (1))
43 /* Set 'Must-set' register */
78 bl pci_write_cfg_byte*/
81 /* Enable NVRAM for environment */
89 /* Init Super-I/O chips */
107 /* Enable configuration mode for SuperIO */
115 bl pci_write_cfg_byte
132 /* Disable configuration mode */
137 bl pci_write_cfg_byte
139 /* Set line control */
140 outb UART(LINE_CONTROL), 0x83
141 outb UART(DIVISOR_LATCH_LSB), 0x0c
142 outb UART(DIVISOR_LATCH_MSB), 0x00
143 outb UART(LINE_CONTROL), 0x3