4 #define GLOBALINFO0 0x50
5 #define GLOBALINFO0_BO (1<<7)
6 #define GLOBALINFO2_B1ARBITER (1<<6)
8 #define HBUSACR2_BURST (1<<0)
9 #define HBUSACR2_LAT (1<<1)
11 #define RECEIVER_HOLDING 0
12 #define TRANSMITTER_HOLDING 0
13 #define INTERRUPT_ENABLE 1
14 #define INTERRUPT_STATUS 2
15 #define FIFO_CONTROL 2
16 #define LINE_CONTROL 3
17 #define MODEM_CONTROL 4
19 #define MODEM_STATUS 6
22 #define DIVISOR_LATCH_LSB 0
23 #define DIVISOR_LATCH_MSB 1
24 #define PRESCALER_DIVISION 5
26 #define UART(x) (0x3f8+(x))
28 #define GLOBALINFO0 0x50
29 #define GLOBALINFO0_BO (1<<7)
30 #define GLOBALINFO2_B1ARBITER (1<<6)
32 #define HBUSACR2_BURST (1<<0)
33 #define HBUSACR2_LAT (1<<1)
35 #define SUPERIO_1 ((7 << 3) | (0))
36 #define SUPERIO_2 ((7 << 3) | (1))
42 /* Set 'Must-set' register */
77 bl pci_write_cfg_byte*/
80 /* Enable NVRAM for environment */
88 /* Init Super-I/O chips */
106 /* Enable configuration mode for SuperIO */
114 bl pci_write_cfg_byte
131 /* Disable configuration mode */
136 bl pci_write_cfg_byte
138 /* Set line control */
139 outb UART(LINE_CONTROL), 0x83
140 outb UART(DIVISOR_LATCH_LSB), 0x0c
141 outb UART(DIVISOR_LATCH_MSB), 0x00
142 outb UART(LINE_CONTROL), 0x3