2 **=====================================================================
4 ** Copyright (C) 2000, 2001, 2002, 2003
5 ** The LEOX team <team@leox.org>, http://www.leox.org
7 ** LEOX.org is about the development of free hardware and software resources
10 ** Description: U-Boot port on the LEOX's ELPT860 CPU board
13 **=====================================================================
15 ** This program is free software; you can redistribute it and/or
16 ** modify it under the terms of the GNU General Public License as
17 ** published by the Free Software Foundation; either version 2 of
18 ** the License, or (at your option) any later version.
20 ** This program is distributed in the hope that it will be useful,
21 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
22 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 ** GNU General Public License for more details.
25 ** You should have received a copy of the GNU General Public License
26 ** along with this program; if not, write to the Free Software
27 ** Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 **=====================================================================
34 ** Note 1: In this file, you have to provide the following functions:
36 ** int board_early_init_f(void)
37 ** int checkboard(void)
38 ** long int initdram(int board_type)
39 ** called from 'board_init_f()' into 'common/board.c'
41 ** void reset_phy(void)
42 ** called from 'board_init_r()' into 'common/board.c'
48 /* ------------------------------------------------------------------------- */
50 static long int dram_size (long int, long int *, long int);
52 /* ------------------------------------------------------------------------- */
54 #define _NOT_USED_ 0xFFFFFFFF
56 const uint init_sdram_table[] = {
58 * Single Read. (Offset 0 in UPMA RAM)
60 0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
61 0xFFFFFC04, /* last */
63 * SDRAM Initialization (offset 5 in UPMA RAM)
65 * This is no UPM entry point. The following definition uses
66 * the remaining space to establish an initialization
67 * sequence, which is executed by a RUN command.
70 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, /* last */
72 * Burst Read. (Offset 8 in UPMA RAM)
74 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
75 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
76 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
77 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
79 * Single Write. (Offset 18 in UPMA RAM)
81 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
82 0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
84 * Burst Write. (Offset 20 in UPMA RAM)
86 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
87 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
88 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
89 0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
92 const uint sdram_table[] = {
94 * Single Read. (Offset 0 in UPMA RAM)
96 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
97 0xFF0FFC00, /* last */
99 * SDRAM Initialization (offset 5 in UPMA RAM)
101 * This is no UPM entry point. The following definition uses
102 * the remaining space to establish an initialization
103 * sequence, which is executed by a RUN command.
106 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */
108 * Burst Read. (Offset 8 in UPMA RAM)
110 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
111 0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
112 0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
113 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
115 * Single Write. (Offset 18 in UPMA RAM)
117 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
118 0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */
121 * Burst Write. (Offset 20 in UPMA RAM)
123 0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
124 0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
125 0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
126 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
128 * Refresh (Offset 30 in UPMA RAM)
130 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
131 0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
132 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
134 * Exception. (Offset 3c in UPMA RAM)
136 0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
139 /* ------------------------------------------------------------------------- */
141 #define CFG_PC4 0x0800
143 #define CFG_DS1 CFG_PC4
146 * Very early board init code (fpga boot, etc.)
148 int board_early_init_f (void)
150 volatile immap_t *immr = (immap_t *) CFG_IMMR;
153 * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
155 immr->im_ioport.iop_pcdat &= ~CFG_DS1; /* PCDAT (DS1 = 0) */
156 immr->im_ioport.iop_pcpar &= ~CFG_DS1; /* PCPAR (0=general purpose I/O) */
157 immr->im_ioport.iop_pcdir |= CFG_DS1; /* PCDIR (I/O: 0=input, 1=output) */
159 return (0); /* success */
163 * Check Board Identity:
165 * Test ELPT860 ID string
167 * Return 1 if no second DRAM bank, otherwise returns 0
170 int checkboard (void)
172 char *s = getenv ("serial#");
174 if (!s || strncmp (s, "ELPT860", 7))
175 printf ("### No HW ID - assuming ELPT860\n");
177 return (0); /* success */
180 /* ------------------------------------------------------------------------- */
182 long int initdram (int board_type)
184 volatile immap_t *immap = (immap_t *) CFG_IMMR;
185 volatile memctl8xx_t *memctl = &immap->im_memctl;
186 long int size8, size9;
187 long int size_b0 = 0;
190 * This sequence initializes SDRAM chips on ELPT860 board
192 upmconfig (UPMA, (uint *) init_sdram_table,
193 sizeof (init_sdram_table) / sizeof (uint));
195 memctl->memc_mptpr = 0x0200;
196 memctl->memc_mamr = 0x18002111;
198 memctl->memc_mar = 0x00000088;
199 memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */
201 upmconfig (UPMA, (uint *) sdram_table,
202 sizeof (sdram_table) / sizeof (uint));
205 * Preliminary prescaler for refresh (depends on number of
206 * banks): This value is selected for four cycles every 62.4 us
207 * with two SDRAM banks or four cycles every 31.2 us with one
208 * bank. It will be adjusted after memory sizing.
210 memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
213 * The following value is used as an address (i.e. opcode) for
214 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
215 * the port size is 32bit the SDRAM does NOT "see" the lower two
216 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
219 * | | | | +- Burst Length = 4
220 * | | | +----- Burst Type = Sequential
221 * | | +------- CAS Latency = 2
222 * | +----------- Operating Mode = Standard
223 * +-------------- Write Burst Mode = Programmed Burst Length
225 memctl->memc_mar = 0x00000088;
228 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
229 * preliminary addresses - these have to be modified after the
230 * SDRAM size has been determined.
232 memctl->memc_or1 = CFG_OR1_PRELIM;
233 memctl->memc_br1 = CFG_BR1_PRELIM;
235 memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
239 /* perform SDRAM initializsation sequence */
241 memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */
243 memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */
246 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
251 * Check Bank 0 Memory Size for re-configuration
255 size8 = dram_size (CFG_MAMR_8COL,
256 SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
263 size9 = dram_size (CFG_MAMR_9COL,
264 SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
266 if (size8 < size9) { /* leave configuration at 9 columns */
268 /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
269 } else { /* back to 8 columns */
272 memctl->memc_mamr = CFG_MAMR_8COL;
274 /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
280 * Adjust refresh rate depending on SDRAM type, both banks
281 * For types > 128 MBit leave it at the current (fast) rate
283 if (size_b0 < 0x02000000) {
284 /* reduce to 15.6 us (62.4 us / quad) */
285 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
290 * Final mapping: map bigger bank first
292 memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
293 memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
298 /* adjust refresh rate depending on SDRAM type, one bank */
299 reg = memctl->memc_mptpr;
300 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
301 memctl->memc_mptpr = reg;
309 /* ------------------------------------------------------------------------- */
312 * Check memory range for valid RAM. A simple memory test determines
313 * the actually available RAM size between addresses `base' and
314 * `base + maxsize'. Some (not all) hardware errors are detected:
315 * - short between address lines
316 * - short between data lines
320 dram_size (long int mamr_value, long int *base, long int maxsize)
322 volatile immap_t *immap = (immap_t *) CFG_IMMR;
323 volatile memctl8xx_t *memctl = &immap->im_memctl;
325 memctl->memc_mamr = mamr_value;
327 return (get_ram_size (base, maxsize));
330 /* ------------------------------------------------------------------------- */
332 #define CFG_PA1 0x4000
333 #define CFG_PA2 0x2000
335 #define CFG_LBKs (CFG_PA2 | CFG_PA1)
337 void reset_phy (void)
339 volatile immap_t *immr = (immap_t *) CFG_IMMR;
342 * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
343 * and no AUI loopback
345 immr->im_ioport.iop_padat &= ~CFG_LBKs; /* PADAT (LBK eth 1&2 = 0) */
346 immr->im_ioport.iop_papar &= ~CFG_LBKs; /* PAPAR (0=general purpose I/O) */
347 immr->im_ioport.iop_padir |= CFG_LBKs; /* PADIR (I/O: 0=input, 1=output) */