1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
4 * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
6 * Derived from the code for
7 * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
19 #include <asm/arch/cpu.h>
20 #include <asm/arch/soc.h>
21 #include <dm/uclass.h>
22 #include <fdt_support.h>
24 #include <linux/bitops.h>
25 #include <u-boot/crc.h>
26 # include <atsha204a-i2c.h>
28 #include "../drivers/ddr/marvell/a38x/ddr3_init.h"
29 #include <../serdes/a38x/high_speed_env_spec.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 #define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
35 #define OMNIA_I2C_MCU_CHIP_ADDR 0x2a
36 #define OMNIA_I2C_MCU_CHIP_LEN 1
38 #define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54
39 #define OMNIA_I2C_EEPROM_CHIP_LEN 2
40 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
43 CMD_GET_STATUS_WORD = 0x01,
45 CMD_WATCHDOG_STATE = 0x0b,
48 enum status_word_bits {
49 CARD_DET_STSBIT = 0x0010,
50 MSATA_IND_STSBIT = 0x0020,
53 #define OMNIA_ATSHA204_OTP_VERSION 0
54 #define OMNIA_ATSHA204_OTP_SERIAL 1
55 #define OMNIA_ATSHA204_OTP_MAC0 3
56 #define OMNIA_ATSHA204_OTP_MAC1 4
59 * Those values and defines are taken from the Marvell U-Boot version
60 * "u-boot-2013.01-2014_T3.0"
62 #define OMNIA_GPP_OUT_ENA_LOW \
63 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
64 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
65 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
66 #define OMNIA_GPP_OUT_ENA_MID \
67 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
68 BIT(16) | BIT(17) | BIT(18)))
70 #define OMNIA_GPP_OUT_VAL_LOW 0x0
71 #define OMNIA_GPP_OUT_VAL_MID 0x0
72 #define OMNIA_GPP_POL_LOW 0x0
73 #define OMNIA_GPP_POL_MID 0x0
75 static struct serdes_map board_serdes_map_pex[] = {
76 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
77 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
78 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
79 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
80 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
81 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
84 static struct serdes_map board_serdes_map_sata[] = {
85 {SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
86 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
87 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
88 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
89 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
90 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
93 static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
96 struct udevice *bus, *dev;
99 ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
101 printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
102 OMNIA_I2C_BUS_NAME, ret);
106 ret = i2c_get_chip(bus, addr, offset_len, &dev);
108 printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
116 static int omnia_mcu_read(u8 cmd, void *buf, int len)
118 struct udevice *chip;
120 chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
121 OMNIA_I2C_MCU_CHIP_LEN);
125 return dm_i2c_read(chip, cmd, buf, len);
128 #ifndef CONFIG_SPL_BUILD
129 static int omnia_mcu_write(u8 cmd, const void *buf, int len)
131 struct udevice *chip;
133 chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
134 OMNIA_I2C_MCU_CHIP_LEN);
138 return dm_i2c_write(chip, cmd, buf, len);
141 static bool disable_mcu_watchdog(void)
145 puts("Disabling MCU watchdog... ");
147 ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
149 printf("omnia_mcu_write failed: %i\n", ret);
159 static bool omnia_detect_sata(void)
164 puts("MiniPCIe/mSATA card detection... ");
166 ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
168 printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
173 if (!(stsword & CARD_DET_STSBIT)) {
178 if (stsword & MSATA_IND_STSBIT)
183 return stsword & MSATA_IND_STSBIT ? true : false;
186 int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
188 if (omnia_detect_sata()) {
189 *serdes_map_array = board_serdes_map_sata;
190 *count = ARRAY_SIZE(board_serdes_map_sata);
192 *serdes_map_array = board_serdes_map_pex;
193 *count = ARRAY_SIZE(board_serdes_map_pex);
199 struct omnia_eeprom {
206 static bool omnia_read_eeprom(struct omnia_eeprom *oep)
208 struct udevice *chip;
212 chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
213 OMNIA_I2C_EEPROM_CHIP_LEN);
218 ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
220 printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
224 if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
225 printf("bad EEPROM magic number (%08x, should be %08x)\n",
226 oep->magic, OMNIA_I2C_EEPROM_MAGIC);
230 crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
231 if (crc != oep->crc) {
232 printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
240 static int omnia_get_ram_size_gb(void)
243 struct omnia_eeprom oep;
246 /* Get the board config from EEPROM */
247 if (omnia_read_eeprom(&oep)) {
248 debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
250 if (oep.ramsize == 0x2)
255 /* Hardcoded fallback */
256 puts("Memory config from EEPROM read failed!\n");
257 puts("Falling back to default 1 GiB!\n");
266 * Define the DDR layout / topology here in the board file. This will
267 * be used by the DDR3 init code in the SPL U-Boot version to configure
268 * the DDR3 controller.
270 static struct mv_ddr_topology_map board_topology_map_1g = {
272 0x1, /* active interfaces */
273 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
274 { { { {0x1, 0, 0, 0},
279 SPEED_BIN_DDR_1600K, /* speed_bin */
280 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
281 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
282 MV_DDR_FREQ_800, /* frequency */
283 0, 0, /* cas_wl cas_l */
284 MV_DDR_TEMP_NORMAL, /* temperature */
285 MV_DDR_TIM_2T} }, /* timing */
286 BUS_MASK_32BIT, /* Busses mask */
287 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
288 { {0} }, /* raw spd data */
289 {0} /* timing parameters */
292 static struct mv_ddr_topology_map board_topology_map_2g = {
294 0x1, /* active interfaces */
295 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
296 { { { {0x1, 0, 0, 0},
301 SPEED_BIN_DDR_1600K, /* speed_bin */
302 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
303 MV_DDR_DIE_CAP_8GBIT, /* mem_size */
304 MV_DDR_FREQ_800, /* frequency */
305 0, 0, /* cas_wl cas_l */
306 MV_DDR_TEMP_NORMAL, /* temperature */
307 MV_DDR_TIM_2T} }, /* timing */
308 BUS_MASK_32BIT, /* Busses mask */
309 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
310 { {0} }, /* raw spd data */
311 {0} /* timing parameters */
314 struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
316 if (omnia_get_ram_size_gb() == 2)
317 return &board_topology_map_2g;
319 return &board_topology_map_1g;
322 #ifndef CONFIG_SPL_BUILD
323 static int set_regdomain(void)
325 struct omnia_eeprom oep;
326 char rd[3] = {' ', ' ', 0};
328 if (omnia_read_eeprom(&oep))
329 memcpy(rd, &oep.region, 2);
331 puts("EEPROM regdomain read failed.\n");
333 printf("Regdomain set to %s\n", rd);
334 return env_set("regdomain", rd);
338 * default factory reset bootcommand on Omnia first sets all the front LEDs
339 * to green and then tries to load the rescue image from SPI flash memory and
342 #define OMNIA_FACTORY_RESET_BOOTCMD \
344 "i2c mw 0x2a.1 0x3 0x1c 1; " \
345 "i2c mw 0x2a.1 0x4 0x1c 1; " \
346 "mw.l 0x01000000 0x00ff000c; " \
347 "i2c write 0x01000000 0x2a.1 0x5 4 -s; " \
348 "setenv bootargs \"earlyprintk console=ttyS0,115200" \
349 " omniarescue=$omnia_reset\"; " \
351 "sf read 0x1000000 0x100000 0x700000; " \
352 "bootm 0x1000000; " \
355 static void handle_reset_button(void)
360 ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
362 printf("omnia_mcu_read failed: %i, reset status unknown!\n",
367 env_set_ulong("omnia_reset", reset_status);
370 printf("RESET button was pressed, overwriting bootcmd!\n");
371 env_set("bootcmd", OMNIA_FACTORY_RESET_BOOTCMD);
376 int board_early_init_f(void)
379 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
380 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
381 writel(0x11244011, MVEBU_MPP_BASE + 0x08);
382 writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
383 writel(0x22200002, MVEBU_MPP_BASE + 0x10);
384 writel(0x30042022, MVEBU_MPP_BASE + 0x14);
385 writel(0x55550555, MVEBU_MPP_BASE + 0x18);
386 writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
388 /* Set GPP Out value */
389 writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
390 writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
392 /* Set GPP Polarity */
393 writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
394 writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
396 /* Set GPP Out Enable */
397 writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
398 writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
405 /* address of boot parameters */
406 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
408 #ifndef CONFIG_SPL_BUILD
409 disable_mcu_watchdog();
415 int board_late_init(void)
417 #ifndef CONFIG_SPL_BUILD
419 handle_reset_button();
426 static struct udevice *get_atsha204a_dev(void)
428 static struct udevice *dev;
433 if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
434 puts("Cannot find ATSHA204A on I2C bus!\n");
443 u32 version_num, serial_num;
446 struct udevice *dev = get_atsha204a_dev();
449 err = atsha204a_wakeup(dev);
453 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
454 OMNIA_ATSHA204_OTP_VERSION,
459 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
460 OMNIA_ATSHA204_OTP_SERIAL,
465 atsha204a_sleep(dev);
469 printf("Turris Omnia:\n");
470 printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
472 printf(" Serial Number: unknown\n");
474 printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num),
475 be32_to_cpu(serial_num));
480 static void increment_mac(u8 *mac)
484 for (i = 5; i >= 3; i--) {
491 int misc_init_r(void)
494 struct udevice *dev = get_atsha204a_dev();
495 u8 mac0[4], mac1[4], mac[6];
500 err = atsha204a_wakeup(dev);
504 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
505 OMNIA_ATSHA204_OTP_MAC0, mac0);
509 err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
510 OMNIA_ATSHA204_OTP_MAC1, mac1);
514 atsha204a_sleep(dev);
523 if (is_valid_ethaddr(mac))
524 eth_env_set_enetaddr("eth1addr", mac);
528 if (is_valid_ethaddr(mac))
529 eth_env_set_enetaddr("eth2addr", mac);
533 if (is_valid_ethaddr(mac))
534 eth_env_set_enetaddr("ethaddr", mac);