board/BuR/brppt1/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for B&R BRPPT1
   6  *
   7  * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at>
   8  * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
   9  *
  10  */
  11
  12 #include <common.h>
  13 #include <env.h>
  14 #include <errno.h>
  15 #include <spl.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/hardware.h>
  18 #include <asm/arch/omap.h>
  19 #include <asm/arch/ddr_defs.h>
  20 #include <asm/arch/clock.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/mem.h>
  24 #include <asm/io.h>
  25 #include <asm/emif.h>
  26 #include <asm/gpio.h>
  27 #include <i2c.h>
  28 #include <power/tps65217.h>
  29 #include "../common/bur_common.h"
  30 #include <watchdog.h>
  31
  32 DECLARE_GLOBAL_DATA_PTR;
  33
  34 /* --------------------------------------------------------------------------*/
  35 /* -- defines for GPIO -- */
  36 #define REPSWITCH       (0+20)  /* GPIO0_20 */
  37
  38 #if defined(CONFIG_SPL_BUILD)
  39 /* TODO: check ram-timing ! */
  40 static const struct ddr_data ddr3_data = {
  41         .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  42         .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  43         .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  44         .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  45 };
  46
  47 static const struct cmd_control ddr3_cmd_ctrl_data = {
  48         .cmd0csratio = MT41K256M16HA125E_RATIO,
  49         .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  50
  51         .cmd1csratio = MT41K256M16HA125E_RATIO,
  52         .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  53
  54         .cmd2csratio = MT41K256M16HA125E_RATIO,
  55         .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  56 };
  57
  58 static struct emif_regs ddr3_emif_reg_data = {
  59         .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  60         .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  61         .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  62         .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  63         .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  64         .zq_config = MT41K256M16HA125E_ZQ_CFG,
  65         .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  66 };
  67
  68 static const struct ctrl_ioregs ddr3_ioregs = {
  69         .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  70         .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  71         .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  72         .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  73         .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  74 };
  75
  76 #define OSC     (V_OSCK/1000000)
  77 static const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1};
  78
  79 void am33xx_spl_board_init(void)
  80 {
  81         int rc;
  82
  83         struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER;
  84         /*struct cm_wkuppll *const cmwkup = (struct cm_wkuppll *)CM_WKUP;*/
  85         struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
  86
  87         /*
  88          * in TRM they write a reset value of 1 (=CLK_M_OSC) for the
  89          * CLKSEL_TIMER6_CLK Register, in fact reset value is 0, so we need set
  90          * the source of timer6 clk to CLK_M_OSC
  91          */
  92         writel(0x01, &cmdpll->clktimer6clk);
  93
  94         /* enable additional clocks of modules which are accessed later */
  95         u32 *const clk_domains[] = {
  96                 &cmper->lcdcclkstctrl,
  97                 0
  98         };
  99
 100         u32 *const clk_modules_tsspecific[] = {
 101                 &cmper->lcdclkctrl,
 102                 &cmper->timer5clkctrl,
 103                 &cmper->timer6clkctrl,
 104                 0
 105         };
 106         do_enable_clocks(clk_domains, clk_modules_tsspecific, 1);
 107
 108         /* setup I2C */
 109         enable_i2c_pin_mux();
 110
 111         pmicsetup(0, 0);
 112
 113         /* peripheral reset */
 114         rc = gpio_request(64 + 29, "GPMC_WAIT1");
 115         if (rc != 0)
 116                 printf("cannot request GPMC_WAIT1 GPIO!\n");
 117         rc = gpio_direction_output(64 + 29, 1);
 118         if (rc != 0)
 119                 printf("cannot set GPMC_WAIT1 GPIO!\n");
 120
 121         rc = gpio_request(64 + 28, "GPMC_WAIT0");
 122         if (rc != 0)
 123                 printf("cannot request GPMC_WAIT0 GPIO!\n");
 124         rc = gpio_direction_output(64 + 28, 1);
 125         if (rc != 0)
 126                 printf("cannot set GPMC_WAIT0 GPIO!\n");
 127
 128 }
 129
 130 const struct dpll_params *get_dpll_ddr_params(void)
 131 {
 132         return &dpll_ddr3;
 133 }
 134
 135 void sdram_init(void)
 136 {
 137         config_ddr(400, &ddr3_ioregs,
 138                    &ddr3_data,
 139                    &ddr3_cmd_ctrl_data,
 140                    &ddr3_emif_reg_data, 0);
 141 }
 142 #endif /* CONFIG_SPL_BUILD */
 143
 144 /* Basic board specific setup.  Pinmux has been handled already. */
 145 int board_init(void)
 146 {
 147 #if defined(CONFIG_HW_WATCHDOG)
 148         hw_watchdog_init();
 149 #endif
 150         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 151 #ifdef CONFIG_NAND
 152         gpmc_init();
 153 #endif
 154         return 0;
 155 }
 156
 157 #ifdef CONFIG_BOARD_LATE_INIT
 158 static char *bootmodeascii[16] = {
 159         "BOOT",         "reserved",     "reserved",     "reserved",
 160         "RUN",          "reserved",     "reserved",     "reserved",
 161         "reserved",     "reserved",     "reserved",     "reserved",
 162         "PME",          "reserved",     "reserved",     "DIAG",
 163 };
 164
 165 int board_late_init(void)
 166 {
 167         unsigned char bmode = 0;
 168         ulong bootcount = 0;
 169         int rc;
 170
 171         bootcount = bootcount_load() & 0xF;
 172
 173         rc = gpio_request(REPSWITCH, "REPSWITCH");
 174
 175         if (rc != 0 || gpio_get_value(REPSWITCH) == 0 || bootcount == 12)
 176                 bmode = 12;
 177         else if (bootcount > 0)
 178                 bmode = 0;
 179         else
 180                 bmode = 4;
 181
 182         printf("Mode:  %s\n", bootmodeascii[bmode & 0x0F]);
 183         env_set_ulong("b_mode", bmode);
 184
 185         /* get sure that bootcmd isn't affected by any bootcount value */
 186         env_set_ulong("bootlimit", 0);
 187
 188         return 0;
 189 }
 190 #endif /* CONFIG_BOARD_LATE_INIT */