board/Arcturus/ucp1020/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2013-2015 Arcturus Networks, Inc.
   4  *           http://www.arcturusnetworks.com/products/ucp1020/
   5  * based on board/freescale/p1_p2_rdb_pc/spl.c
   6  * original copyright follows:
   7  * Copyright 2013 Freescale Semiconductor, Inc.
   8  */
   9
  10 #include <common.h>
  11 #include <asm/mmu.h>
  12 #include <asm/immap_85xx.h>
  13 #include <asm/processor.h>
  14 #include <fsl_ddr_sdram.h>
  15 #include <fsl_ddr_dimm_params.h>
  16 #include <asm/io.h>
  17 #include <asm/fsl_law.h>
  18
  19 #ifdef CONFIG_SYS_DDR_RAW_TIMING
  20 #if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1)
  21 /*
  22  * Micron MT41J128M16HA-15E
  23  * */
  24 dimm_params_t ddr_raw_timing = {
  25         .n_ranks = 1,
  26         .rank_density = 536870912u,
  27         .capacity = 536870912u,
  28         .primary_sdram_width = 32,
  29         .ec_sdram_width = 8,
  30         .registered_dimm = 0,
  31         .mirrored_dimm = 0,
  32         .n_row_addr = 14,
  33         .n_col_addr = 10,
  34         .n_banks_per_sdram_device = 8,
  35         .edc_config = 2,
  36         .burst_lengths_bitmask = 0x0c,
  37
  38         .tckmin_x_ps = 1650,
  39         .caslat_x = 0x7e << 4,  /* 5,6,7,8,9,10 */
  40         .taa_ps = 14050,
  41         .twr_ps = 15000,
  42         .trcd_ps = 13500,
  43         .trrd_ps = 75000,
  44         .trp_ps = 13500,
  45         .tras_ps = 40000,
  46         .trc_ps = 49500,
  47         .trfc_ps = 160000,
  48         .twtr_ps = 75000,
  49         .trtp_ps = 75000,
  50         .refresh_rate_ps = 7800000,
  51         .tfaw_ps = 30000,
  52 };
  53
  54 #else
  55 #error Missing raw timing data for this board
  56 #endif
  57
  58 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  59                             unsigned int controller_number,
  60                             unsigned int dimm_number)
  61 {
  62         const char dimm_model[] = "Fixed DDR on board";
  63
  64         if ((controller_number == 0) && (dimm_number == 0)) {
  65                 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  66                 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  67                 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  68         }
  69
  70         return 0;
  71 }
  72 #endif /* CONFIG_SYS_DDR_RAW_TIMING */
  73
  74 #ifdef CONFIG_SYS_DDR_CS0_BNDS
  75 /* Fixed sdram init -- doesn't use serial presence detect. */
  76 phys_size_t fixed_sdram(void)
  77 {
  78         sys_info_t sysinfo;
  79         char buf[32];
  80         size_t ddr_size;
  81         fsl_ddr_cfg_regs_t ddr_cfg_regs = {
  82                 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  83                 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  84                 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  85 #if CONFIG_CHIP_SELECTS_PER_CTRL > 1
  86                 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
  87                 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
  88                 .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
  89 #endif
  90                 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
  91                 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
  92                 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
  93                 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
  94                 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
  95                 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
  96                 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
  97                 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
  98                 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  99                 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
 100                 .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
 101                 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
 102                 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
 103                 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
 104                 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
 105                 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
 106                 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
 107                 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
 108                 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
 109                 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
 110                 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
 111         };
 112
 113         get_sys_info(&sysinfo);
 114         printf("Configuring DDR for %s MT/s data rate\n",
 115                strmhz(buf, sysinfo.freq_ddrbus));
 116
 117         ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 118
 119         fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
 120
 121         if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
 122                          ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
 123                 printf("ERROR setting Local Access Windows for DDR\n");
 124                 return 0;
 125         };
 126
 127         return ddr_size;
 128 }
 129 #endif
 130
 131 void fsl_ddr_board_options(memctl_options_t *popts,
 132                            dimm_params_t *pdimm,
 133                            unsigned int ctrl_num)
 134 {
 135         int i;
 136
 137         popts->clk_adjust = 6;
 138         popts->cpo_override = 0x1f;
 139         popts->write_data_delay = 2;
 140         popts->half_strength_driver_enable = 1;
 141         /* Write leveling override */
 142         popts->wrlvl_en = 1;
 143         popts->wrlvl_override = 1;
 144         popts->wrlvl_sample = 0xf;
 145         popts->wrlvl_start = 0x8;
 146         popts->trwt_override = 1;
 147         popts->trwt = 0;
 148
 149         if (pdimm->primary_sdram_width == 64)
 150                 popts->data_bus_width = 0;
 151         else if (pdimm->primary_sdram_width == 32)
 152                 popts->data_bus_width = 1;
 153         else
 154                 printf("Error in DDR bus width configuration!\n");
 155
 156         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 157                 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
 158                 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
 159         }
 160 }