2 * Based on Linux/Xtensa kernel version
4 * Copyright (C) 2001 - 2007 Tensilica Inc.
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef _XTENSA_BYTEORDER_H
10 #define _XTENSA_BYTEORDER_H
12 #include <asm/types.h>
14 static inline __attribute__((const)) __u32 ___arch__swab32(__u32 x)
18 /* instruction sequence from Xtensa ISA release 2/2000 */
30 static inline __attribute__((const)) __u16 ___arch__swab16(__u16 x)
33 * Given that 'short' values are signed (i.e., can be negative),
34 * we cannot assume that the upper 16-bits of the register are
35 * zero. We are careful to mask values after shifting.
39 * There exists an anomaly between xt-gcc and xt-xcc. xt-gcc
40 * inserts an extui instruction after putting this function inline
41 * to ensure that it uses only the least-significant 16 bits of
42 * the result. xt-xcc doesn't use an extui, but assumes the
43 * __asm__ macro follows convention that the upper 16 bits of an
44 * 'unsigned short' result are still zero. This macro doesn't
45 * follow convention; indeed, it leaves garbage in the upport 16
46 * bits of the register.
48 * Declaring the temporary variables 'res' and 'tmp' to be 32-bit
49 * types while the return type of the function is a 16-bit type
50 * forces both compilers to insert exactly one extui instruction
51 * (or equivalent) to mask off the upper 16 bits.
57 __asm__("extui %1, %2, 8, 8\n\t"
60 : "=&a" (res), "=&a" (tmp)
67 #define __arch__swab32(x) ___arch__swab32(x)
68 #define __arch__swab16(x) ___arch__swab16(x)
70 #if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
71 # define __BYTEORDER_HAS_U64__
72 # define __SWAB_64_THRU_32__
76 # include <linux/byteorder/little_endian.h>
77 #elif defined(__XTENSA_EB__)
78 # include <linux/byteorder/big_endian.h>
80 # error processor byte order undefined!
83 #endif /* _XTENSA_BYTEORDER_H */