2 * Copyright (C) 2008-2013 Tensilica Inc.
3 * Copyright (C) 2016 Cadence Design Systems Inc.
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _XTENSA_ADDRSPACE_H
9 #define _XTENSA_ADDRSPACE_H
11 #include <asm/arch/core.h>
16 * noMMU and v3 MMU have identity mapped address space on reset.
18 * IO (uncached) f0000000..ffffffff -> f000000
19 * IO (cached) e0000000..efffffff -> f000000
20 * MEM (uncached) d8000000..dfffffff -> 0000000
21 * MEM (cached) d0000000..d7ffffff -> 0000000
23 * The actual location of memory and IO is the board property.
26 #define IOADDR(x) (CONFIG_SYS_IO_BASE + (x))
27 #define MEMADDR(x) (CONFIG_SYS_MEMORY_BASE + (x))
28 #define PHYSADDR(x) ((x) - XCHAL_VECBASE_RESET_VADDR + \
29 XCHAL_VECBASE_RESET_PADDR)
31 #endif /* _XTENSA_ADDRSPACE_H */