2 * Copyright (c) 2012 The Chromium OS Authors.
4 * TSC calibration codes are adapted from Linux kernel
5 * arch/x86/kernel/tsc_msr.c and arch/x86/kernel/tsc.c
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/i8254.h>
14 #include <asm/ibmpc.h>
16 #include <asm/u-boot-x86.h>
18 /* CPU reference clock frequency: in KHz */
20 #define FREQ_100 99840
21 #define FREQ_133 133200
22 #define FREQ_166 166400
24 #define MAX_NUM_FREQS 8
26 DECLARE_GLOBAL_DATA_PTR;
29 * According to Intel 64 and IA-32 System Programming Guide,
30 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
31 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
32 * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
33 * so we need manually differentiate SoC families. This is what the
34 * field msr_plat does.
37 u8 x86_family; /* CPU family */
38 u8 x86_model; /* model */
39 /* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
41 u32 freqs[MAX_NUM_FREQS];
44 static struct freq_desc freq_desc_tables[] = {
46 { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
48 { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
50 { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
52 { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
54 { 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
56 { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
59 static int match_cpu(u8 family, u8 model)
63 for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
64 if ((family == freq_desc_tables[i].x86_family) &&
65 (model == freq_desc_tables[i].x86_model))
72 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
73 #define id_to_freq(cpu_index, freq_id) \
74 (freq_desc_tables[cpu_index].freqs[freq_id])
77 * Do MSR calibration only for known/supported CPUs.
79 * Returns the calibration value or 0 if MSR calibration failed.
81 static unsigned long try_msr_calibrate_tsc(void)
83 u32 lo, hi, ratio, freq_id, freq;
87 cpu_index = match_cpu(gd->arch.x86, gd->arch.x86_model);
91 if (freq_desc_tables[cpu_index].msr_plat) {
92 rdmsr(MSR_PLATFORM_INFO, lo, hi);
93 ratio = (lo >> 8) & 0x1f;
95 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
96 ratio = (hi >> 8) & 0x1f;
98 debug("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
103 if (freq_desc_tables[cpu_index].msr_plat == 2) {
104 /* TODO: Figure out how best to deal with this */
106 debug("Using frequency: %u KHz\n", freq);
108 /* Get FSB FREQ ID */
109 rdmsr(MSR_FSB_FREQ, lo, hi);
111 freq = id_to_freq(cpu_index, freq_id);
112 debug("Resolved frequency ID: %u, frequency: %u KHz\n",
118 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
119 res = freq * ratio / 1000;
120 debug("TSC runs at %lu MHz\n", res);
125 debug("Fast TSC calibration using MSR failed\n");
130 * This reads the current MSB of the PIT counter, and
131 * checks if we are running on sufficiently fast and
132 * non-virtualized hardware.
134 * Our expectations are:
136 * - the PIT is running at roughly 1.19MHz
138 * - each IO is going to take about 1us on real hardware,
139 * but we allow it to be much faster (by a factor of 10) or
140 * _slightly_ slower (ie we allow up to a 2us read+counter
141 * update - anything else implies a unacceptably slow CPU
142 * or PIT for the fast calibration to work.
144 * - with 256 PIT ticks to read the value, we have 214us to
145 * see the same MSB (and overhead like doing a single TSC
146 * read per MSB value etc).
148 * - We're doing 2 reads per loop (LSB, MSB), and we expect
149 * them each to take about a microsecond on real hardware.
150 * So we expect a count value of around 100. But we'll be
151 * generous, and accept anything over 50.
153 * - if the PIT is stuck, and we see *many* more reads, we
154 * return early (and the next caller of pit_expect_msb()
155 * then consider it a failure when they don't see the
156 * next expected value).
158 * These expectations mean that we know that we have seen the
159 * transition from one expected value to another with a fairly
160 * high accuracy, and we didn't miss any events. We can thus
161 * use the TSC value at the transitions to calculate a pretty
162 * good value for the TSC frequencty.
164 static inline int pit_verify_msb(unsigned char val)
168 return inb(0x42) == val;
171 static inline int pit_expect_msb(unsigned char val, u64 *tscp,
172 unsigned long *deltap)
175 u64 tsc = 0, prev_tsc = 0;
177 for (count = 0; count < 50000; count++) {
178 if (!pit_verify_msb(val))
183 *deltap = rdtsc() - prev_tsc;
187 * We require _some_ success, but the quality control
188 * will be based on the error terms on the TSC values.
194 * How many MSB values do we want to see? We aim for
195 * a maximum error rate of 500ppm (in practice the
196 * real error is much smaller), but refuse to spend
197 * more than 50ms on it.
199 #define MAX_QUICK_PIT_MS 50
200 #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
202 static unsigned long quick_pit_calibrate(void)
206 unsigned long d1, d2;
208 /* Set the Gate high, disable speaker */
209 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
212 * Counter 2, mode 0 (one-shot), binary count
214 * NOTE! Mode 2 decrements by two (and then the
215 * output is flipped each time, giving the same
216 * final output frequency as a decrement-by-one),
217 * so mode 0 is much better when looking at the
222 /* Start at 0xffff */
227 * The PIT starts counting at the next edge, so we
228 * need to delay for a microsecond. The easiest way
229 * to do that is to just read back the 16-bit counter
234 if (pit_expect_msb(0xff, &tsc, &d1)) {
235 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
236 if (!pit_expect_msb(0xff-i, &delta, &d2))
240 * Iterate until the error is less than 500 ppm
243 if (d1+d2 >= delta >> 11)
247 * Check the PIT one more time to verify that
248 * all TSC reads were stable wrt the PIT.
250 * This also guarantees serialization of the
251 * last cycle read ('d2') in pit_expect_msb.
253 if (!pit_verify_msb(0xfe - i))
258 debug("Fast TSC calibration failed\n");
263 * Ok, if we get here, then we've seen the
264 * MSB of the PIT decrement 'i' times, and the
265 * error has shrunk to less than 500 ppm.
267 * As a result, we can depend on there not being
268 * any odd delays anywhere, and the TSC reads are
269 * reliable (within the error).
271 * kHz = ticks / time-in-seconds / 1000;
272 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
273 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
275 delta *= PIT_TICK_RATE;
276 delta /= (i*256*1000);
277 debug("Fast TSC calibration using PIT\n");
281 void timer_set_base(u64 base)
283 gd->arch.tsc_base = base;
287 * Get the number of CPU time counter ticks since it was read first time after
288 * restart. This yields a free running counter guaranteed to take almost 6
289 * years to wrap around even at 100GHz clock rate.
291 u64 __attribute__((no_instrument_function)) get_ticks(void)
293 u64 now_tick = rdtsc();
295 /* We assume that 0 means the base hasn't been set yet */
296 if (!gd->arch.tsc_base)
297 panic("No tick base available");
298 return now_tick - gd->arch.tsc_base;
301 /* Get the speed of the TSC timer in MHz */
302 unsigned __attribute__((no_instrument_function)) long get_tbclk_mhz(void)
304 unsigned long fast_calibrate;
306 if (gd->arch.tsc_mhz)
307 return gd->arch.tsc_mhz;
309 fast_calibrate = try_msr_calibrate_tsc();
310 if (!fast_calibrate) {
312 fast_calibrate = quick_pit_calibrate();
314 panic("TSC frequency is ZERO");
317 gd->arch.tsc_mhz = fast_calibrate;
318 return fast_calibrate;
321 unsigned long get_tbclk(void)
323 return get_tbclk_mhz() * 1000 * 1000;
326 static ulong get_ms_timer(void)
328 return (get_ticks() * 1000) / get_tbclk();
331 ulong get_timer(ulong base)
333 return get_ms_timer() - base;
336 ulong __attribute__((no_instrument_function)) timer_get_us(void)
338 return get_ticks() / get_tbclk_mhz();
341 ulong timer_get_boot_us(void)
343 return timer_get_us();
346 void __udelay(unsigned long usec)
348 u64 now = get_ticks();
351 stop = now + usec * get_tbclk_mhz();
353 while ((int64_t)(stop - get_ticks()) > 0)
359 #ifdef CONFIG_SYS_PCAT_TIMER
360 /* Set up the PCAT timer if required */