1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Google, Inc
7 #include <debug_uart.h>
13 #include <asm/processor.h>
14 #include <asm-generic/sections.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 __weak int arch_cpu_init_dm(void)
23 static int x86_tpl_init(void)
27 debug("%s starting\n", __func__);
28 ret = x86_cpu_init_tpl();
30 debug("%s: x86_cpu_init_tpl() failed\n", __func__);
35 debug("%s: spl_init() failed\n", __func__);
38 ret = arch_cpu_init();
40 debug("%s: arch_cpu_init() failed\n", __func__);
43 ret = arch_cpu_init_dm();
45 debug("%s: arch_cpu_init_dm() failed\n", __func__);
48 preloader_console_init();
53 void board_init_f(ulong flags)
59 debug("Error %d\n", ret);
60 panic("x86_tpl_init fail");
63 /* Uninit CAR and jump to board_init_f_r() */
67 void board_init_f_r(void)
69 /* Not used since we never call board_init_f_r_trampoline() */
73 u32 spl_boot_device(void)
75 return IS_ENABLED(CONFIG_CHROMEOS) ? BOOT_DEVICE_CROS_VBOOT :
79 int spl_start_uboot(void)
84 void spl_board_announce_boot_device(void)
89 static int spl_board_load_image(struct spl_image_info *spl_image,
90 struct spl_boot_device *bootdev)
92 spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
93 spl_image->entry_point = CONFIG_SPL_TEXT_BASE;
94 spl_image->load_addr = CONFIG_SPL_TEXT_BASE;
95 spl_image->os = IH_OS_U_BOOT;
96 spl_image->name = "U-Boot";
98 debug("Loading to %lx\n", spl_image->load_addr);
102 SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
104 int spl_spi_load_image(void)
109 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
111 debug("Jumping to U-Boot SPL at %lx\n", (ulong)spl_image->entry_point);
112 jump_to_spl(spl_image->entry_point);
116 void spl_board_init(void)
118 preloader_console_init();
121 #if !CONFIG_IS_ENABLED(PCI)
123 * This is a fake PCI bus for TPL when it doesn't have proper PCI. It is enough
124 * to bind the devices on the PCI bus, some of which have early-regs properties
125 * providing fixed BARs. Individual drivers program these BARs themselves so
126 * that they can access the devices. The BARs are allocated statically in the
129 * Once SPL is running it enables PCI properly, but does not auto-assign BARs
130 * for devices, so the TPL BARs continue to be used. Once U-Boot starts it does
131 * the auto allocation (after relocation).
133 static const struct udevice_id tpl_fake_pci_ids[] = {
134 { .compatible = "pci-x86" },
138 U_BOOT_DRIVER(pci_x86) = {
140 .id = UCLASS_SIMPLE_BUS,
141 .of_match = tpl_fake_pci_ids,