1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 Google, Inc
8 #include <debug_uart.h>
14 #include <asm/cpu_common.h>
15 #include <asm/mrccache.h>
18 #include <asm/processor.h>
20 #include <asm-generic/sections.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 __weak int arch_cpu_init_dm(void)
31 static int set_max_freq(void)
33 if (cpu_get_burst_mode_state() == BURST_MODE_UNAVAILABLE) {
35 * Burst Mode has been factory-configured as disabled and is not
36 * available in this physical processor package
38 debug("Burst Mode is factory-disabled\n");
42 /* Enable burst mode */
43 cpu_set_burst_mode(true);
45 /* Enable speed step */
48 /* Set P-State ratio */
49 cpu_set_p_state_to_turbo_ratio();
55 static int x86_spl_init(void)
59 * TODO(sjg@chromium.org): We use this area of RAM for the stack
60 * and global_data in SPL. Once U-Boot starts up and releocates it
61 * is not needed. We could make this a CONFIG option or perhaps
62 * place it immediately below CONFIG_SYS_TEXT_BASE.
64 char *ptr = (char *)0x110000;
66 struct udevice *punit;
70 debug("%s starting\n", __func__);
72 ret = x86_cpu_reinit_f();
74 ret = x86_cpu_init_f();
77 debug("%s: spl_init() failed\n", __func__);
80 ret = arch_cpu_init();
82 debug("%s: arch_cpu_init() failed\n", __func__);
86 ret = arch_cpu_init_dm();
88 debug("%s: arch_cpu_init_dm() failed\n", __func__);
92 preloader_console_init();
94 ret = print_cpuinfo();
96 debug("%s: print_cpuinfo() failed\n", __func__);
102 debug("%s: dram_init() failed\n", __func__);
105 if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {
106 ret = mrccache_spl_save();
108 debug("%s: Failed to write to mrccache (err=%d)\n",
113 memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
115 /* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
116 ret = interrupt_init();
118 debug("%s: interrupt_init() failed\n", __func__);
123 * The stack grows down from ptr. Put the global data at ptr. This
124 * will only be used for SPL. Once SPL loads U-Boot proper it will
125 * set up its own stack.
127 gd->new_gd = (struct global_data *)ptr;
128 memcpy(gd->new_gd, gd, sizeof(*gd));
129 arch_setup_gd(gd->new_gd);
130 gd->start_addr_sp = (ulong)ptr;
132 /* Cache the SPI flash. Otherwise copying the code to RAM takes ages */
133 ret = mtrr_add_request(MTRR_TYPE_WRBACK,
134 (1ULL << 32) - CONFIG_XIP_ROM_SIZE,
135 CONFIG_XIP_ROM_SIZE);
137 debug("%s: SPI cache setup failed (err=%d)\n", __func__, ret);
142 ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit);
144 debug("Could not find PUNIT (err=%d)\n", ret);
146 ret = set_max_freq();
148 debug("Failed to set CPU frequency (err=%d)\n", ret);
154 void board_init_f(ulong flags)
158 ret = x86_spl_init();
160 debug("Error %d\n", ret);
161 panic("x86_spl_init fail");
164 gd->bd = malloc(sizeof(*gd->bd));
166 printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd));
171 /* Uninit CAR and jump to board_init_f_r() */
172 board_init_f_r_trampoline(gd->start_addr_sp);
176 void board_init_f_r(void)
179 gd->flags &= ~GD_FLG_SERIAL_READY;
180 debug("cache status %d\n", dcache_status());
184 u32 spl_boot_device(void)
186 return BOOT_DEVICE_SPI_MMAP;
189 int spl_start_uboot(void)
194 void spl_board_announce_boot_device(void)
199 static int spl_board_load_image(struct spl_image_info *spl_image,
200 struct spl_boot_device *bootdev)
202 spl_image->size = CONFIG_SYS_MONITOR_LEN;
203 spl_image->entry_point = CONFIG_SYS_TEXT_BASE;
204 spl_image->load_addr = CONFIG_SYS_TEXT_BASE;
205 spl_image->os = IH_OS_U_BOOT;
206 spl_image->name = "U-Boot";
208 debug("Loading to %lx\n", spl_image->load_addr);
212 SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
214 int spl_spi_load_image(void)
219 #ifdef CONFIG_X86_RUN_64BIT
220 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
224 printf("Jumping to 64-bit U-Boot: Note many features are missing\n");
225 ret = cpu_jump_to_64bit_uboot(spl_image->entry_point);
226 debug("ret=%d\n", ret);
231 void spl_board_init(void)
234 preloader_console_init();